Volume 2B Instruction Set Reference N-Z (794102), страница 30
Текст из файла (страница 30)
2B 4-209INSTRUCTION SET REFERENCE, N-ZDEST[95:64] ← DEST[127:96];DEST[127:96] ← SRC[127:96];PUNPCKHQDQ instruction:DEST[63:0] ← DEST[127:64];DEST[127:64] ← SRC[127:64];Intel C/C++ Compiler Intrinsic EquivalentsPUNPCKHBW__m64 _mm_unpackhi_pi8(__m64 m1, __m64 m2)PUNPCKHBW__m128i _mm_unpackhi_epi8(__m128i m1, __m128i m2)PUNPCKHWD__m64 _mm_unpackhi_pi16(__m64 m1,__m64 m2)PUNPCKHWD__m128i _mm_unpackhi_epi16(__m128i m1,__m128i m2)PUNPCKHDQ__m64 _mm_unpackhi_pi32(__m64 m1, __m64 m2)PUNPCKHDQ__m128i _mm_unpackhi_epi32(__m128i m1, __m128i m2)PUNPCKHQDQ__m128i _mm_unpackhi_epi64 ( __m128i a, __m128i b)Flags AffectedNone.Numeric ExceptionsNone.Protected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.(128-bit operations only) If a memory operand is not aligned ona 16-byte boundary, regardless of segment.#SS(0)If a memory operand effective address is outside the SSsegment limit.#UDIf CR0.EM[bit 2] = 1.(128-bit operations only) If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made while the current privilegelevel is 3.4-210 Vol.
2BPUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ— Unpack High DataINSTRUCTION SET REFERENCE, N-ZReal-Address Mode Exceptions#GP(0)If any part of the operand lies outside of the effective addressspace from 0 to FFFFH.(128-bit operations only) If a memory operand is not aligned ona 16-byte boundary, regardless of segment.#UDIf CR0.EM[bit 2] = 1.(128-bit operations only) If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.(128-bit version only) If memory operand is not aligned on a16-byte boundary, regardless of segment.#UDIf CR0.EM[bit 2] = 1.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made while the current privilegelevel is 3.PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ— Unpack High DataVol.
2B 4-211INSTRUCTION SET REFERENCE, N-ZPUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ—Unpack Low DataOpcodeInstruction64-BitModeCompat/Leg ModeDescription0F 60 /rPUNPCKLBW mm,mm/m32ValidValidInterleave low-order bytes frommm and mm/m32 into mm.66 0F 60 /rPUNPCKLBW xmm1,xmm2/m128ValidValidInterleave low-order bytes fromxmm1 and xmm2/m128 intoxmm1.0F 61 /rPUNPCKLWD mm,mm/m32ValidValidInterleave low-order words frommm and mm/m32 into mm.66 0F 61 /rPUNPCKLWD xmm1,xmm2/m128ValidValidInterleave low-order words fromxmm1 and xmm2/m128 intoxmm1.0F 62 /rPUNPCKLDQ mm,mm/m32ValidValidInterleave low-order doublewordsfrom mm and mm/m32 into mm.66 0F 62 /rPUNPCKLDQ xmm1,xmm2/m128ValidValidInterleave low-order doublewordsfrom xmm1 and xmm2/m128 intoxmm1.66 0F 6C /rPUNPCKLQDQ xmm1,xmm2/m128ValidValidInterleave low-order quadwordfrom xmm1 and xmm2/m128 intoxmm1 register.DescriptionUnpacks and interleaves the low-order data elements (bytes, words, doublewords,and quadwords) of the destination operand (first operand) and source operand(second operand) into the destination operand.
(Figure 4-12 shows the unpack operation for bytes in 64-bit operands.). The high-order data elements are ignored.SRC Y7 Y6Y5 Y4Y3 Y2Y1 Y0X7 X6DEST Y3 X3 Y2X5 X4X2 Y1X3 X2X1 Y0X1 X0 DESTX0Figure 4-12. PUNPCKLBW Instruction Operation Using 64-bit Operands4-212 Vol. 2BPUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ— Unpack Low DataINSTRUCTION SET REFERENCE, N-ZThe source operand can be an MMX technology register or a 32-bit memory location,or it can be an XMM register or a 128-bit memory location. The destination operandcan be an MMX technology register or an XMM register.
When the source data comesfrom a 128-bit memory operand, an implementation may fetch only the appropriate64 bits; however, alignment to a 16-byte boundary and normal segment checkingwill still be enforced.The PUNPCKLBW instruction interleaves the low-order bytes of the source and destination operands, the PUNPCKLWD instruction interleaves the low-order words of thesource and destination operands, the PUNPCKLDQ instruction interleaves the loworder doubleword (or doublewords) of the source and destination operands, and thePUNPCKLQDQ instruction interleaves the low-order quadwords of the source anddestination operands.These instructions can be used to convert bytes to words, words to doublewords,doublewords to quadwords, and quadwords to double quadwords, respectively, byplacing all 0s in the source operand. Here, if the source operand contains all 0s, theresult (stored in the destination operand) contains zero extensions of the high-orderdata elements from the original value in the destination operand.
For example, withthe PUNPCKLBW instruction the high-order bytes are zero extended (that is,unpacked into unsigned word integers), and with the PUNPCKLWD instruction, thehigh-order words are zero extended (unpacked into unsigned doubleword integers).In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction toaccess additional registers (XMM8-XMM15).OperationPUNPCKLBW instruction with 64-bit operands:DEST[63:56] ← SRC[31:24];DEST[55:48] ← DEST[31:24];DEST[47:40] ← SRC[23:16];DEST[39:32] ← DEST[23:16];DEST[31:24] ← SRC[15:8];DEST[23:16] ← DEST[15:8];DEST[15:8] ← SRC[7:0];DEST[7:0] ← DEST[7:0];PUNPCKLWD instruction with 64-bit operands:DEST[63:48] ← SRC[31:16];DEST[47:32] ← DEST[31:16];DEST[31:16] ← SRC[15:0];DEST[15:0] ← DEST[15:0];PUNPCKLDQ instruction with 64-bit operands:DEST[63:32] ← SRC[31:0];DEST[31:0] ← DEST[31:0];PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ— Unpack Low DataVol.
2B 4-213INSTRUCTION SET REFERENCE, N-ZPUNPCKLBW instruction with 128-bit operands:DEST[7:0]← DEST[7:0];DEST[15:8] ← SRC[7:0];DEST[23:16] ← DEST[15:8];DEST[31:24] ← SRC[15:8];DEST[39:32] ← DEST[23:16];DEST[47:40] ← SRC[23:16];DEST[55:48] ← DEST[31:24];DEST[63:56] ← SRC[31:24];DEST[71:64] ← DEST[39:32];DEST[79:72] ← SRC[39:32];DEST[87:80] ← DEST[47:40];DEST[95:88] ← SRC[47:40];DEST[103:96] ← DEST[55:48];DEST[111:104] ← SRC[55:48];DEST[119:112] ← DEST[63:56];DEST[127:120] ← SRC[63:56];PUNPCKLWD instruction with 128-bit operands:DEST[15:0] ← DEST[15:0];DEST[31:16] ← SRC[15:0];DEST[47:32] ← DEST[31:16];DEST[63:48] ← SRC[31:16];DEST[79:64] ← DEST[47:32];DEST[95:80] ← SRC[47:32];DEST[111:96] ← DEST[63:48];DEST[127:112] ← SRC[63:48];PUNPCKLDQ instruction with 128-bit operands:DEST[31:0] ← DEST[31:0];DEST[63:32] ← SRC[31:0];DEST[95:64] ← DEST[63:32];DEST[127:96] ← SRC[63:32];PUNPCKLQDQDEST[63:0] ← DEST[63:0];DEST[127:64] ← SRC[63:0];Intel C/C++ Compiler Intrinsic EquivalentsPUNPCKLBW__m64 _mm_unpacklo_pi8 (__m64 m1, __m64 m2)PUNPCKLBW__m128i _mm_unpacklo_epi8 (__m128i m1, __m128i m2)PUNPCKLWD__m64 _mm_unpacklo_pi16 (__m64 m1, __m64 m2)PUNPCKLWD__m128i _mm_unpacklo_epi16 (__m128i m1, __m128i m2)4-214 Vol.
2BPUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ— Unpack Low DataINSTRUCTION SET REFERENCE, N-ZPUNPCKLDQ__m64 _mm_unpacklo_pi32 (__m64 m1, __m64 m2)PUNPCKLDQ__m128i _mm_unpacklo_epi32 (__m128i m1, __m128i m2)PUNPCKLQDQ__m128i _mm_unpacklo_epi64 (__m128i m1, __m128i m2)Flags AffectedNone.Numeric ExceptionsNone.Protected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.(128-bit operations only) If a memory operand is not aligned ona 16-byte boundary, regardless of segment.#SS(0)If a memory operand effective address is outside the SSsegment limit.#UDIf CR0.EM[bit 2] = 1.(128-bit operations only) If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made while the current privilegelevel is 3.Real-Address Mode Exceptions#GP(0)If any part of the operand lies outside of the effective addressspace from 0 to 0FFFFH.(128-bit operations only) If a memory operand is not aligned ona 16-byte boundary, regardless of segment.#UDIf CR0.EM[bit 2] = 1.(128-bit operations only) If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ— Unpack Low DataVol.
2B 4-215INSTRUCTION SET REFERENCE, N-ZVirtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)#GP(0)If a memory address referencing the SS segment is in a noncanonical form.If the memory address is in a non-canonical form.(128-bit version only) If memory operand is not aligned on a16-byte boundary, regardless of segment.#UDIf CR0.EM[bit 2] = 1.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made while the current privilegelevel is 3.4-216 Vol.
2BPUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ— Unpack Low DataINSTRUCTION SET REFERENCE, N-ZPUSH—Push Word, Doubleword or Quadword Onto the StackOpcode*Instruction64-BitModeCompat/Leg ModeDescriptionFF /6PUSH r/m16ValidValidPush r/m16.FF /6PUSH r/m32N.E.ValidPush r/m32.FF /6PUSH r/m64ValidN.E.Push r/m64. Default operand size 64bits.50+rwPUSH r16ValidValidPush r16.50+rdPUSH r32N.E.ValidPush r32.50+rdPUSH r64ValidN.E.Push r64. Default operand size64-bits.6APUSH imm8ValidValidPush sign-extended imm8.
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