Volume 2B Instruction Set Reference N-Z (794102), страница 33
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Uses a 6 bit count.C1 /2 ibRCL r/m32,imm8ValidValidRotate 33 bits (CF, r/m32) left imm8times.REX.W + C1 /2ibRCL r/m64,imm8ValidN.E.Rotate 65 bits (CF, r/m64) left imm8times. Uses a 6 bit count.D0 /3RCR r/m8, 1ValidValidRotate 9 bits (CF, r/m8) right once.REX + D0 /3RCR r/m8*, 1ValidN.E.Rotate 9 bits (CF, r/m8) right once.D2 /3RCR r/m8, CLValidValidRotate 9 bits (CF, r/m8) right CLtimes.REX + D2 /3RCR r/m8*, CLValidN.E.Rotate 9 bits (CF, r/m8) right CLtimes.RCL/RCR/ROL/ROR-—RotateVol.
2B 4-231INSTRUCTION SET REFERENCE, N-ZOpcode**Instruction64-BitModeCompat/Leg ModeDescriptionC0 /3 ibRCR r/m8,imm8ValidValidRotate 9 bits (CF, r/m8) right imm8times.REX + C0 /3 ibRCR r/m8*,imm8ValidN.E.Rotate 9 bits (CF, r/m8) right imm8times.D1 /3RCR r/m16, 1ValidValidRotate 17 bits (CF, r/m16) right once.D3 /3RCR r/m16, CLValidValidRotate 17 bits (CF, r/m16) right CLtimes.C1 /3 ibRCR r/m16,imm8ValidValidRotate 17 bits (CF, r/m16) right imm8times.D1 /3RCR r/m32, 1ValidValidRotate 33 bits (CF, r/m32) right once.Uses a 6 bit count.REX.W + D1 /3RCR r/m64, 1ValidN.E.Rotate 65 bits (CF, r/m64) right once.Uses a 6 bit count.D3 /3RCR r/m32, CLValidValidRotate 33 bits (CF, r/m32) right CLtimes.REX.W + D3 /3RCR r/m64, CLValidN.E.Rotate 65 bits (CF, r/m64) right CLtimes.
Uses a 6 bit count.C1 /3 ibRCR r/m32,imm8ValidValidRotate 33 bits (CF, r/m32) right imm8times.REX.W + C1 /3ibRCR r/m64,imm8ValidN.E.Rotate 65 bits (CF, r/m64) right imm8times. Uses a 6 bit count.D0 /0ROL r/m8, 1ValidValidRotate 8 bits r/m8 left once.REX + D0 /0ROL r/m8*, 1ValidN.E.Rotate 8 bits r/m8 left onceD2 /0ROL r/m8, CLValidValidRotate 8 bits r/m8 left CL times.REX + D2 /0ROL r/m8*, CLValidN.E.Rotate 8 bits r/m8 left CL times.C0 /0 ibROL r/m8,imm8ValidValidRotate 8 bits r/m8 left imm8 times.REX + C0 /0 ibROL r/m8*,imm8ValidN.E.Rotate 8 bits r/m8 left imm8 times.D1 /0ROL r/m16, 1ValidValidRotate 16 bits r/m16 left once.D3 /0ROL r/m16, CLValidValidRotate 16 bits r/m16 left CL times.C1 /0 ibROL r/m16,imm8ValidValidRotate 16 bits r/m16 left imm8times.D1 /0ROL r/m32, 1ValidValidRotate 32 bits r/m32 left once.4-232 Vol.
2BRCL/RCR/ROL/ROR-—RotateINSTRUCTION SET REFERENCE, N-ZOpcode**Instruction64-BitModeCompat/Leg ModeDescriptionREX.W + D1 /0ROL r/m64, 1ValidN.E.Rotate 64 bits r/m64 left once. Usesa 6 bit count.D3 /0ROL r/m32, CLValidValidRotate 32 bits r/m32 left CL times.REX.W + D3 /0ROL r/m64, CLValidN.E.Rotate 64 bits r/m64 left CL times.Uses a 6 bit count.C1 /0 ibROL r/m32,imm8ValidValidRotate 32 bits r/m32 left imm8times.C1 /0 ibROL r/m64,imm8ValidN.E.Rotate 64 bits r/m64 left imm8times. Uses a 6 bit count.D0 /1ROR r/m8, 1ValidValidRotate 8 bits r/m8 right once.REX + D0 /1ROR r/m8*, 1ValidN.E.Rotate 8 bits r/m8 right once.D2 /1ROR r/m8, CLValidValidRotate 8 bits r/m8 right CL times.REX + D2 /1ROR r/m8*, CLValidN.E.Rotate 8 bits r/m8 right CL times.C0 /1 ibROR r/m8,imm8ValidValidRotate 8 bits r/m16 right imm8times.REX + C0 /1 ibROR r/m8*,imm8ValidN.E.Rotate 8 bits r/m16 right imm8times.D1 /1ROR r/m16, 1ValidValidRotate 16 bits r/m16 right once.D3 /1ROR r/m16, CLValidValidRotate 16 bits r/m16 right CL times.C1 /1 ibROR r/m16,imm8ValidValidRotate 16 bits r/m16 right imm8times.D1 /1ROR r/m32, 1ValidValidRotate 32 bits r/m32 right once.REX.W + D1 /1ROR r/m64, 1ValidN.E.Rotate 64 bits r/m64 right once.
Usesa 6 bit count.D3 /1ROR r/m32, CLValidValidRotate 32 bits r/m32 right CL times.REX.W + D3 /1ROR r/m64, CLValidN.E.Rotate 64 bits r/m64 right CL times.Uses a 6 bit count.C1 /1 ibROR r/m32,imm8ValidValidRotate 32 bits r/m32 right imm8times.REX.W + C1 /1ibROR r/m64,imm8ValidN.E.Rotate 64 bits r/m64 right imm8times. Uses a 6 bit count.NOTES:* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix isused: AH, BH, CH, DH.** See IA-32 Architecture Compatibility section below.RCL/RCR/ROL/ROR-—RotateVol. 2B 4-233INSTRUCTION SET REFERENCE, N-ZDescriptionShifts (rotates) the bits of the first operand (destination operand) the number of bitpositions specified in the second operand (count operand) and stores the result in thedestination operand.
The destination operand can be a register or a memory location; the count operand is an unsigned integer that can be an immediate or a value inthe CL register. In legacy and compatibility mode, the processor restricts the count toa number between 0 and 31 by masking all the bits in the count operand except the5 least-significant bits.The rotate left (ROL) and rotate through carry left (RCL) instructions shift all the bitstoward more-significant bit positions, except for the most-significant bit, which isrotated to the least-significant bit location.
The rotate right (ROR) and rotate throughcarry right (RCR) instructions shift all the bits toward less significant bit positions,except for the least-significant bit, which is rotated to the most-significant bit location.The RCL and RCR instructions include the CF flag in the rotation. The RCL instructionshifts the CF flag into the least-significant bit and shifts the most-significant bit intothe CF flag. The RCR instruction shifts the CF flag into the most-significant bit andshifts the least-significant bit into the CF flag.
For the ROL and ROR instructions, theoriginal value of the CF flag is not a part of the result, but the CF flag receives a copyof the bit that was shifted from one end to the other.The OF flag is defined only for the 1-bit rotates; it is undefined in all other cases(except that a zero-bit rotate does nothing, that is affects no flags).
For left rotates,the OF flag is set to the exclusive OR of the CF bit (after the rotate) and the mostsignificant bit of the result. For right rotates, the OF flag is set to the exclusive OR ofthe two most-significant bits of the result.In 64-bit mode, using a REX prefix in the form of REX.R permits access to additionalregisters (R8-R15). Use of REX.W promotes the first operand to 64 bits and causesthe count operand to become a 6-bit counter.IA-32 Architecture CompatibilityThe 8086 does not mask the rotation count. However, all other IA-32 processors(starting with the Intel 286 processor) do mask the rotation count to 5 bits, resultingin a maximum count of 31. This masking is done in all operating modes (including thevirtual-8086 mode) to reduce the maximum execution time of the instructions.Operation(* RCL and RCR instructions *)SIZE ← OperandSize;CASE (determine count) OFSIZE ← 8:tempCOUNT ← (COUNT AND 1FH) MOD 9;SIZE ← 16: tempCOUNT ← (COUNT AND 1FH) MOD 17;SIZE ← 32: tempCOUNT ← COUNT AND 1FH;4-234 Vol.
2BRCL/RCR/ROL/ROR-—RotateINSTRUCTION SET REFERENCE, N-ZSIZE ← 64:ESAC;tempCOUNT ← COUNT AND 3FH;(* RCL instruction operation *)WHILE (tempCOUNT ≠ 0)DOtempCF ← MSB(DEST);DEST ← (DEST ∗ 2) + CF;CF ← tempCF;tempCOUNT ← tempCOUNT – 1;OD;ELIHW;IF COUNT = 1THEN OF ← MSB(DEST) XOR CF;ELSE OF is undefined;FI;(* RCR instruction operation *)IF COUNT = 1THEN OF ← MSB(DEST) XOR CF;ELSE OF is undefined;FI;WHILE (tempCOUNT ≠ 0)DOtempCF ← LSB(SRC);DEST ← (DEST / 2) + (CF * 2SIZE);CF ← tempCF;tempCOUNT ← tempCOUNT – 1;OD;(* ROL and ROR instructions *)SIZE ← OperandSize;CASE (determine count) OFSIZE ← 8:tempCOUNT ← (COUNT AND 1FH) MOD 8; (* Mask count before MOD *)SIZE ← 16: tempCOUNT ← (COUNT AND 1FH) MOD 16;SIZE ← 32: tempCOUNT ← (COUNT AND 1FH) MOD 32;SIZE ← 64: tempCOUNT ← (COUNT AND 1FH) MOD 64;ESAC;(* ROL instruction operation *)IF (tempCOUNT > 0) (* Prevents updates to CF *)WHILE (tempCOUNT ≠ 0)DORCL/RCR/ROL/ROR-—RotateVol.
2B 4-235INSTRUCTION SET REFERENCE, N-ZtempCF ← MSB(DEST);DEST ← (DEST ∗ 2) + tempCF;tempCOUNT ← tempCOUNT – 1;OD;ELIHW;CF ← LSB(DEST);IF COUNT = 1THEN OF ← MSB(DEST) XOR CF;ELSE OF is undefined;FI;FI;(* ROR instruction operation *)IF tempCOUNT > 0) (* Prevent updates to CF *)WHILE (tempCOUNT ≠ 0)DOtempCF ← LSB(SRC);DEST ← (DEST / 2) + (tempCF ∗ 2SIZE);tempCOUNT ← tempCOUNT – 1;OD;ELIHW;CF ← MSB(DEST);IF COUNT = 1THEN OF ← MSB(DEST) XOR MSB − 1(DEST);ELSE OF is undefined;FI;FI;Flags AffectedThe CF flag contains the value of the bit shifted into it. The OF flag is affected only forsingle-bit rotates (see “Description” above); it is undefined for multi-bit rotates.
TheSF, ZF, AF, and PF flags are not affected.Protected Mode Exceptions#GP(0)If the source operand is located in a non-writable segment.If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register contains a NULL segmentselector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.4-236 Vol. 2BRCL/RCR/ROL/ROR-—RotateINSTRUCTION SET REFERENCE, N-Z#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.#UDIf the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.#UDIf the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)#GP(0)If a memory address referencing the SS segment is in a noncanonical form.If the source operand is located in a nonwritable segment.If the memory address is in a non-canonical form.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.RCL/RCR/ROL/ROR-—RotateVol.
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