Volume 2B Instruction Set Reference N-Z (794102), страница 32
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2B 4-223INSTRUCTION SET REFERENCE, N-ZCompatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#UD4-224 Vol. 2BIf in 64-bit mode.PUSHA/PUSHAD—Push All General-Purpose RegistersINSTRUCTION SET REFERENCE, N-ZPUSHF/PUSHFD—Push EFLAGS Register onto the StackOpcodeInstruction64-BitModeCompat/Leg ModeDescription9CPUSHFValidValidPush lower 16 bits of EFLAGS.9CPUSHFDN.E.ValidPush EFLAGS.9CPUSHFQValidN.E.Push RFLAGS.DescriptionDecrements the stack pointer by 4 (if the current operand-size attribute is 32) andpushes the entire contents of the EFLAGS register onto the stack, or decrements thestack pointer by 2 (if the operand-size attribute is 16) and pushes the lower 16 bitsof the EFLAGS register (that is, the FLAGS register) onto the stack.
These instructions reverse the operation of the POPF/POPFD instructions.When copying the entire EFLAGS register to the stack, the VM and RF flags (bits 16and 17) are not copied; instead, the values for these flags are cleared in the EFLAGSimage stored on the stack. See Chapter 3 of the Intel® 64 and IA-32 ArchitecturesSoftware Developer’s Manual, Volume 1, for more information about the EFLAGSregister.The PUSHF (push flags) and PUSHFD (push flags double) mnemonics reference thesame opcode. The PUSHF instruction is intended for use when the operand-sizeattribute is 16 and the PUSHFD instruction for when the operand-size attribute is 32.Some assemblers may force the operand size to 16 when PUSHF is used and to 32when PUSHFD is used. Others may treat these mnemonics as synonyms(PUSHF/PUSHFD) and use the current setting of the operand-size attribute to determine the size of values to be pushed from the stack, regardless of the mnemonicused.In 64-bit mode, the instruction’s default operation is to decrement the stack pointer(RSP) by 8 and pushs RFLAGS on the stack.
16-bit operation is supported using theoperand size override prefix 66H. 32-bit operand size cannot be encoded in thismode. When copying RFLAGS to the stack, the VM and RF flags (bits 16 and 17) arenot copied; instead, values for these flags are cleared in the RFLAGS image stored onthe stack.When in virtual-8086 mode and the I/O privilege level (IOPL) is less than 3, thePUSHF/PUSHFD instruction causes a general protection exception (#GP).In the real-address mode, if the ESP or SP register is 1 when PUSHF/PUSHFD instruction executes: an #SS exception is generated but not delivered (the stack errorreported prevents #SS delivery). Next, the processor generates a #DF exception andenters a shutdown state as described in the #DF discussion in Chapter 5 of theIntel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.PUSHF/PUSHFD—Push EFLAGS Register onto the StackVol. 2B 4-225INSTRUCTION SET REFERENCE, N-ZOperationIF (PE = 0) or (PE = 1 and ((VM = 0) or (VM = 1 and IOPL = 3)))(* Real-Address Mode, Protected mode, or Virtual-8086 mode with IOPL equal to 3 *)THENIF OperandSize = 32THENpush (EFLAGS AND 00FCFFFFH);(* VM and RF EFLAG bits are cleared in image stored on the stack *)ELSEpush (EFLAGS); (* Lower 16 bits only *)FI;ELSE IF 64-bit MODE (* In 64-bit Mode *)IF OperandSize = 64THENpush (RFLAGS AND 00000000_00FCFFFFH);(* VM and RF RFLAG bits are cleared in image stored on the stack; *)ELSEpush (EFLAGS); (* Lower 16 bits only *)FI;ELSE (* In Virtual-8086 Mode with IOPL less than 3 *)#GP(0); (* Trap to virtual-8086 monitor *)FI;Flags AffectedNone.Protected Mode Exceptions#SS(0)If the new value of the ESP register is outside the stack segmentboundary.#PF(fault-code)If a page fault occurs.#AC(0)If an unaligned memory reference is made while the currentprivilege level is 3 and alignment checking is enabled.#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#UDIf the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)4-226 Vol.
2BIf the I/O privilege level is less than 3.PUSHF/PUSHFD—Push EFLAGS Register onto the StackINSTRUCTION SET REFERENCE, N-Z#PF(fault-code)If a page fault occurs.#AC(0)If an unaligned memory reference is made while alignmentchecking is enabled.#UDIf the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#GP(0)If the memory address is in a non-canonical form.#SS(0)If the stack address is in a non-canonical form.#PF(fault-code)If a page fault occurs.#AC(0)If an unaligned memory reference is made while the currentprivilege level is 3 and alignment checking is enabled.#UDIf the LOCK prefix is used.PUSHF/PUSHFD—Push EFLAGS Register onto the StackVol. 2B 4-227INSTRUCTION SET REFERENCE, N-ZPXOR—Logical Exclusive OROpcodeInstruction64-BitModeCompat/Leg ModeDescription0F EF /rPXOR mm, mm/m64ValidValidBitwise XOR ofmm/m64 and mm.66 0F EF /rPXOR xmm1, xmm2/m128ValidValidBitwise XOR ofxmm2/m128 andxmm1.DescriptionPerforms a bitwise logical exclusive-OR (XOR) operation on the source operand(second operand) and the destination operand (first operand) and stores the result inthe destination operand.
The source operand can be an MMX technology register or a64-bit memory location or it can be an XMM register or a 128-bit memory location.The destination operand can be an MMX technology register or an XMM register. Eachbit of the result is 1 if the corresponding bits of the two operands are different; eachbit is 0 if the corresponding bits of the operands are the same.In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction toaccess additional registers (XMM8-XMM15).OperationDEST ← DEST XOR SRC;Intel C/C++ Compiler Intrinsic EquivalentPXOR__m64 _mm_xor_si64 (__m64 m1, __m64 m2)PXOR__m128i _mm_xor_si128 ( __m128i a, __m128i b)Flags AffectedNone.Numeric ExceptionsNone.Protected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.(128-bit operations only) If a memory operand is not aligned ona 16-byte boundary, regardless of segment.4-228 Vol.
2BPXOR—Logical Exclusive ORINSTRUCTION SET REFERENCE, N-Z#SS(0)#UDIf a memory operand effective address is outside the SSsegment limit.If CR0.EM[bit 2] = 1.(128-bit operations only) If CR4.OSFXSR[bit 9] = 0.(128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made while the current privilegelevel is 3.Real-Address Mode Exceptions#GP(0)(128-bit operations only) If a memory operand is not aligned ona 16-byte boundary, regardless of segment.If any part of the operand lies outside of the effective addressspace from 0 to FFFFH.#UDIf CR0.EM[bit 2] = 1.(128-bit operations only) If CR4.OSFXSR[bit 9] = 0.(128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.PXOR—Logical Exclusive ORVol.
2B 4-229INSTRUCTION SET REFERENCE, N-Z(128-bit operations only) If memory operand is not aligned on a16-byte boundary, regardless of segment.#UDIf CR0.EM[bit 2] = 1.(128-bit operations only) If CR4.OSFXSR[bit 9] = 0.(128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made while the current privilegelevel is 3.4-230 Vol. 2BPXOR—Logical Exclusive ORINSTRUCTION SET REFERENCE, N-ZRCL/RCR/ROL/ROR-—RotateOpcode**Instruction64-BitModeCompat/Leg ModeDescriptionD0 /2RCL r/m8, 1ValidValidRotate 9 bits (CF, r/m8) left once.REX + D0 /2RCL r/m8*, 1ValidN.E.Rotate 9 bits (CF, r/m8) left once.D2 /2RCL r/m8, CLValidValidRotate 9 bits (CF, r/m8) left CL times.REX + D2 /2RCL r/m8*, CLValidN.E.Rotate 9 bits (CF, r/m8) left CL times.C0 /2 ibRCL r/m8,imm8ValidValidRotate 9 bits (CF, r/m8) left imm8times.REX + C0 /2 ibRCL r/m8*,imm8ValidN.E.Rotate 9 bits (CF, r/m8) left imm8times.D1 /2RCL r/m16, 1ValidValidRotate 17 bits (CF, r/m16) left once.D3 /2RCL r/m16, CLValidValidRotate 17 bits (CF, r/m16) left CLtimes.C1 /2 ibRCL r/m16,imm8ValidValidRotate 17 bits (CF, r/m16) left imm8times.D1 /2RCL r/m32, 1ValidValidRotate 33 bits (CF, r/m32) left once.REX.W + D1 /2RCL r/m64, 1ValidN.E.Rotate 65 bits (CF, r/m64) left once.Uses a 6 bit count.D3 /2RCL r/m32, CLValidValidRotate 33 bits (CF, r/m32) left CLtimes.REX.W + D3 /2RCL r/m64, CLValidN.E.Rotate 65 bits (CF, r/m64) left CLtimes.
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