Volume 2B Instruction Set Reference N-Z (794102), страница 27
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2B 4-191INSTRUCTION SET REFERENCE, N-ZPSUBB/PSUBW/PSUBD—Subtract Packed IntegersOpcodeInstruction64-BitModeCompat/Leg ModeDescription0F F8 /rPSUBB mm,mm/m64ValidValidSubtract packed byte integers inmm/m64 from packed byte integers inmm.66 0F F8 /rPSUBB xmm1,xmm2/m128ValidValidSubtract packed byte integers inxmm2/m128 from packed byteintegers in xmm1.0F F9 /rPSUBW mm,mm/m64ValidValidSubtract packed word integers inmm/m64 from packed word integers inmm.66 0F F9 /rPSUBW xmm1,xmm2/m128ValidValidSubtract packed word integers inxmm2/m128 from packed wordintegers in xmm1.0F FA /rPSUBD mm,mm/m64ValidValidSubtract packed doubleword integersin mm/m64 from packed doublewordintegers in mm.66 0F FA /rPSUBD xmm1,xmm2/m128ValidValidSubtract packed doubleword integersin xmm2/mem128 from packeddoubleword integers in xmm1.DescriptionPerforms a SIMD subtract of the packed integers of the source operand (secondoperand) from the packed integers of the destination operand (first operand), andstores the packed integer results in the destination operand.
See Figure 9-4 in theIntel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for anillustration of a SIMD operation. Overflow is handled with wraparound, as describedin the following paragraphs.These instructions can operate on either 64-bit or 128-bit operands. When operatingon 64-bit operands, the destination operand must be an MMX technology registerand the source operand can be either an MMX technology register or a 64-bitmemory location. When operating on 128-bit operands, the destination operandmust be an XMM register and the source operand can be either an XMM register or a128-bit memory location.The PSUBB instruction subtracts packed byte integers. When an individual result istoo large or too small to be represented in a byte, the result is wrapped around andthe low 8 bits are written to the destination element.The PSUBW instruction subtracts packed word integers. When an individual result istoo large or too small to be represented in a word, the result is wrapped around andthe low 16 bits are written to the destination element.4-192 Vol.
2BPSUBB/PSUBW/PSUBD—Subtract Packed IntegersINSTRUCTION SET REFERENCE, N-ZThe PSUBD instruction subtracts packed doubleword integers. When an individualresult is too large or too small to be represented in a doubleword, the result iswrapped around and the low 32 bits are written to the destination element.Note that the PSUBB, PSUBW, and PSUBD instructions can operate on eitherunsigned or signed (two's complement notation) packed integers; however, it doesnot set bits in the EFLAGS register to indicate overflow and/or a carry.
To preventundetected overflow conditions, software must control the ranges of values uponwhich it operates.In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction toaccess additional registers (XMM8-XMM15).OperationPSUBB instruction with 64-bit operands:DEST[7:0] ← DEST[7:0] − SRC[7:0];(* Repeat subtract operation for 2nd through 7th byte *)DEST[63:56] ← DEST[63:56] − SRC[63:56];PSUBB instruction with 128-bit operands:DEST[7:0] ← DEST[7:0] − SRC[7:0];(* Repeat subtract operation for 2nd through 14th byte *)DEST[127:120] ← DEST[111:120] − SRC[127:120];PSUBW instruction with 64-bit operands:DEST[15:0] ← DEST[15:0] − SRC[15:0];(* Repeat subtract operation for 2nd and 3rd word *)DEST[63:48] ← DEST[63:48] − SRC[63:48];PSUBW instruction with 128-bit operands:DEST[15:0] ← DEST[15:0] − SRC[15:0];(* Repeat subtract operation for 2nd through 7th word *)DEST[127:112] ← DEST[127:112] − SRC[127:112];PSUBD instruction with 64-bit operands:DEST[31:0] ← DEST[31:0] − SRC[31:0];DEST[63:32] ← DEST[63:32] − SRC[63:32];PSUBD instruction with 128-bit operands:DEST[31:0] ← DEST[31:0] − SRC[31:0];(* Repeat subtract operation for 2nd and 3rd doubleword *)DEST[127:96] ← DEST[127:96] − SRC[127:96];Intel C/C++ Compiler Intrinsic EquivalentsPSUBB__m64 _mm_sub_pi8(__m64 m1, __m64 m2)PSUBB/PSUBW/PSUBD—Subtract Packed IntegersVol.
2B 4-193INSTRUCTION SET REFERENCE, N-ZPSUBW__m64 _mm_sub_pi16(__m64 m1, __m64 m2)PSUBD__m64 _mm_sub_pi32(__m64 m1, __m64 m2)PSUBB__m128i _mm_sub_epi8 ( __m128i a, __m128i b)PSUBW__m128i _mm_sub_epi16 ( __m128i a, __m128i b)PSUBD__m128i _mm_sub_epi32 ( __m128i a, __m128i b)Flags AffectedNone.Numeric ExceptionsNone.Protected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.(128-bit operations only) If a memory operand is not aligned ona 16-byte boundary, regardless of segment.#SS(0)#UDIf a memory operand effective address is outside the SSsegment limit.If CR0.EM[bit 2] = 1.(128-bit operations only) If CR4.OSFXSR[bit 9] = 0.(128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made while the current privilegelevel is 3.Real-Address Mode Exceptions#GP(0)(128-bit operations only) If a memory operand is not aligned ona 16-byte boundary, regardless of segment.If any part of the operand lies outside of the effective addressspace from 0 to FFFFH.#UDIf CR0.EM[bit 2] = 1.(128-bit operations only) If CR4.OSFXSR[bit 9] = 0.(128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.4-194 Vol.
2BPSUBB/PSUBW/PSUBD—Subtract Packed IntegersINSTRUCTION SET REFERENCE, N-Z#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made.Compatibility Mode ExceptionsSame as for protected mode exceptions.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.(128-bit operations only) If memory operand is not aligned on a16-byte boundary, regardless of segment.#UDIf CR0.EM[bit 2] = 1.(128-bit operations only) If CR4.OSFXSR[bit 9] = 0.(128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made while the current privilegelevel is 3.PSUBB/PSUBW/PSUBD—Subtract Packed IntegersVol.
2B 4-195INSTRUCTION SET REFERENCE, N-ZPSUBQ—Subtract Packed Quadword IntegersOpcodeInstruction64-BitModeCompat/Leg ModeDescription0F FB /rPSUBQ mm1, mm2/m64ValidValidSubtract quadword integerin mm1 from mm2 /m64.66 0F FB /rPSUBQ xmm1, xmm2/m128 ValidValidSubtract packed quadwordintegers in xmm1 fromxmm2 /m128.DescriptionSubtracts the second operand (source operand) from the first operand (destinationoperand) and stores the result in the destination operand. The source operand can bea quadword integer stored in an MMX technology register or a 64-bit memory location, or it can be two packed quadword integers stored in an XMM register or an128-bit memory location. The destination operand can be a quadword integer storedin an MMX technology register or two packed quadword integers stored in an XMMregister.
When packed quadword operands are used, a SIMD subtract is performed.When a quadword result is too large to be represented in 64 bits (overflow), theresult is wrapped around and the low 64 bits are written to the destination element(that is, the carry is ignored).Note that the PSUBQ instruction can operate on either unsigned or signed (two’scomplement notation) integers; however, it does not set bits in the EFLAGS registerto indicate overflow and/or a carry. To prevent undetected overflow conditions, software must control the ranges of the values upon which it operates.In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction toaccess additional registers (XMM8-XMM15).OperationPSUBQ instruction with 64-Bit operands:DEST[63:0] ← DEST[63:0] − SRC[63:0];PSUBQ instruction with 128-Bit operands:DEST[63:0] ← DEST[63:0] − SRC[63:0];DEST[127:64] ← DEST[127:64] − SRC[127:64];Intel C/C++ Compiler Intrinsic EquivalentsPSUBQ__m64 _mm_sub_si64(__m64 m1, __m64 m2)PSUBQ__m128i _mm_sub_epi64(__m128i m1, __m128i m2)4-196 Vol.
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