Volume 2B Instruction Set Reference N-Z (794102), страница 31
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Stackpointer is incremented by the size ofstack pointer.68PUSH imm16ValidValidPush sign-extended imm16. Stackpointer is incremented by the size ofstack pointer.68PUSH imm32ValidValidPush sign-extended imm32. Stackpointer is incremented by the size ofstack pointer.0EPUSH CSInvalidValidPush CS.16PUSH SSInvalidValidPush SS.1EPUSH DSInvalidValidPush DS.06PUSH ESInvalidValidPush ES.0F A0PUSH FSValidValidPush FS and decrement stack pointerby 16 bits.0F A0PUSH FSN.E.ValidPush FS and decrement stack pointerby 32 bits.0F A0PUSH FSValidN.E.Push FS.
Default operand size 64-bits.(66H override causes 16-bitoperation).0F A8PUSH GSValidValidPush GS and decrement stack pointerby 16 bits.0F A8PUSH GSN.E.ValidPush GS and decrement stack pointerby 32 bits.PUSH—Push Word, Doubleword or Quadword Onto the StackVol. 2B 4-217INSTRUCTION SET REFERENCE, N-ZOpcode*Instruction64-BitModeCompat/Leg ModeDescription0F A8PUSH GSValidN.E.Push GS, default operand size 64-bits.(66H override causes 16-bitoperation).NOTES:* See IA-32 Architecture Compatibility section below.DescriptionDecrements the stack pointer and then stores the source operand on the top of thestack. The address-size attribute of the stack segment determines the stack pointersize (16, 32 or 64 bits).
The operand-size attribute of the current code segmentdetermines the amount the stack pointer is decremented (2, 4 or 8 bytes).In non-64-bit modes: if the address-size and operand-size attributes are 32, the32-bit ESP register (stack pointer) is decremented by 4. If both attributes are 16, the16-bit SP register (stack pointer) is decremented by 2.If the source operand is an immediate and its size is less than the address size of thestack, a sign-extended value is pushed on the stack. If the source operand is the FSor GS and its size is less than the address size of the stack, the zero-extended valueis pushed on the stack.The B flag in the stack segment’s segment descriptor determines the stack’s addresssize attribute.
The D flag in the current code segment’s segment descriptor (withprefixes), determines the operand-size attribute and the address-size attribute of thesource operand. Pushing a 16-bit operand when the stack address-size attribute is 32can result in a misaligned stack pointer (a stack pointer that is not be aligned on adoubleword boundary).The PUSH ESP instruction pushes the value of the ESP register as it existed beforethe instruction was executed. Thus if a PUSH instruction uses a memory operand inwhich the ESP register is used for computing the operand address, the address of theoperand is computed before the ESP register is decremented.In the real-address mode, if the ESP or SP register is 1 when the PUSH instruction isexecuted, an #SS exception is generated but not delivered (the stack error reportedprevents #SS delivery). Next, the processor generates a #DF exception and enters ashutdown state as described in the #DF discussion in Chapter 5 of the Intel® 64 andIA-32 Architectures Software Developer’s Manual, Volume 3A.In 64-bit mode, the instruction’s default operation size is 64 bits.
In a push, the64-bit RSP register (stack pointer) is decremented by 8. A 66H override causes16-bit operation. Note that pushing a 16-bit operand can result in the stack pointermisaligned to 8-byte boundary.4-218 Vol. 2BPUSH—Push Word, Doubleword or Quadword Onto the StackINSTRUCTION SET REFERENCE, N-ZIA-32 Architecture CompatibilityFor IA-32 processors from the Intel 286 on, the PUSH ESP instruction pushes thevalue of the ESP register as it existed before the instruction was executed. (This isalso true for Intel 64 architecture, real-address and virtual-8086 modes of IA-32architecture.) For the Intel® 8086 processor, the PUSH SP instruction pushes the newvalue of the SP register (that is the value after it has been decremented by 2).OperationIF StackAddrSize = 64THENIF OperandSize = 64THENRSP ← (RSP − 8);IF (SRC is FS or GS)THENTEMP = ZeroExtend64(SRC);ELSE IF (SRC is IMMEDIATE)TEMP = SignExtend64(SRC); FI;ELSETEMP = SRC;FIRSP ← TEMP; (* Push quadword *)ELSE (* OperandSize = 16; 66H used *)RSP ← (RSP − 2);RSP ← SRC; (* Push word *)FI;ELSE IF StackAddrSize = 32THENIF OperandSize = 32THENESP ← (ESP − 4);IF (SRC is FS or GS)THENTEMP = ZeroExtend32(SRC);ELSE IF (SRC is IMMEDIATE)TEMP = SignExtend32(SRC); FI;ELSETEMP = SRC;FI;SS:ESP ← TEMP; (* Push doubleword *)ELSE (* OperandSize = 16*)ESP ← (ESP − 2);SS:ESP ← SRC; (* Push word *)PUSH—Push Word, Doubleword or Quadword Onto the StackVol.
2B 4-219INSTRUCTION SET REFERENCE, N-ZFI;ELSE StackAddrSize = 16IF OperandSize = 16THENSP ← (SP − 2);SS:SP ← SRC; (* Push word *)ELSE (* OperandSize = 32 *)SP ← (SP − 4);SS:SP ← SRC; (* Push doubleword *)FI;FI;FI;Flags AffectedNone.Protected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register is used to access memory and itcontains a NULL segment selector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.If the new value of the SP or ESP register is outside the stacksegment limit.#UDIf the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)4-220 Vol.
2BIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.PUSH—Push Word, Doubleword or Quadword Onto the StackINSTRUCTION SET REFERENCE, N-Z#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.#UDIf the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#GP(0)If the memory address is in a non-canonical form.#SS(U)If the stack address is in a non-canonical form.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.PUSH—Push Word, Doubleword or Quadword Onto the StackVol.
2B 4-221INSTRUCTION SET REFERENCE, N-ZPUSHA/PUSHAD—Push All General-Purpose RegistersOpcodeInstruction64-BitModeCompat/Leg ModeDescription60PUSHAInvalidValidPush AX, CX, DX, BX, original SP, BP, SI, andDI.60PUSHADInvalidValidPush EAX, ECX, EDX, EBX, original ESP, EBP,ESI, and EDI.DescriptionPushes the contents of the general-purpose registers onto the stack. The registersare stored on the stack in the following order: EAX, ECX, EDX, EBX, ESP (originalvalue), EBP, ESI, and EDI (if the current operand-size attribute is 32) and AX, CX, DX,BX, SP (original value), BP, SI, and DI (if the operand-size attribute is 16). Theseinstructions perform the reverse operation of the POPA/POPAD instructions.
Thevalue pushed for the ESP or SP register is its value before prior to pushing the firstregister (see the “Operation” section below).The PUSHA (push all) and PUSHAD (push all double) mnemonics reference the sameopcode. The PUSHA instruction is intended for use when the operand-size attribute is16 and the PUSHAD instruction for when the operand-size attribute is 32.
Someassemblers may force the operand size to 16 when PUSHA is used and to 32 whenPUSHAD is used. Others may treat these mnemonics as synonyms (PUSHA/PUSHAD)and use the current setting of the operand-size attribute to determine the size ofvalues to be pushed from the stack, regardless of the mnemonic used.In the real-address mode, if the ESP or SP register is 1, 3, or 5 when PUSHA/PUSHADexecutes: an #SS exception is generated but not delivered (the stack error reportedprevents #SS delivery).
Next, the processor generates a #DF exception and enters ashutdown state as described in the #DF discussion in Chapter 5 of the Intel® 64 andIA-32 Architectures Software Developer’s Manual, Volume 3A.This instruction executes as described in compatibility mode and legacy mode. It isnot valid in 64-bit mode.OperationIF 64-bit ModeTHEN #UDFI;IF OperandSize = 32 (* PUSHAD instruction *)THENTemp ← (ESP);Push(EAX);4-222 Vol. 2BPUSHA/PUSHAD—Push All General-Purpose RegistersINSTRUCTION SET REFERENCE, N-ZPush(ECX);Push(EDX);Push(EBX);Push(Temp);Push(EBP);Push(ESI);Push(EDI);ELSE (* OperandSize = 16, PUSHA instruction *)Temp ← (SP);Push(AX);Push(CX);Push(DX);Push(BX);Push(Temp);Push(BP);Push(SI);Push(DI);FI;Flags AffectedNone.Protected Mode Exceptions#SS(0)If the starting or ending stack address is outside the stacksegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If an unaligned memory reference is made while the currentprivilege level is 3 and alignment checking is enabled.#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#GPIf the ESP or SP register contains 7, 9, 11, 13, or 15.#UDIf the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)If the ESP or SP register contains 7, 9, 11, 13, or 15.#PF(fault-code)If a page fault occurs.#AC(0)If an unaligned memory reference is made while alignmentchecking is enabled.#UDIf the LOCK prefix is used.PUSHA/PUSHAD—Push All General-Purpose RegistersVol.
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