Volume 2B Instruction Set Reference N-Z (794102), страница 35
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2B 4-245INSTRUCTION SET REFERENCE, N-ZRDPMC—Read Performance-Monitoring CountersOpcodeInstruction64-BitModeCompat/Leg ModeDescription0F 33RDPMCValidValidRead performance-monitoringcounter specified by ECX intoEDX:EAX.DescriptionLoads the 40-bit performance-monitoring counter specified in the ECX register intoregisters EDX:EAX. (On processors that support the Intel 64 architecture, the highorder 32 bits of RCX are ignored.) The EDX register is loaded with the high-order 8bits of the counter and the EAX register is loaded with the low-order 32 bits. (Onprocessors that support the Intel 64 architecture, the high-order 32 bits of each ofRAX and RDX are cleared.) See below for the treatment of the EDX register for “fast”reads.The indices used to specify performance counters are model-specific and may varyby processor implementations.
See Table 4-2 for valid indices for each processorfamily.Table 4-2. Valid Performance Counter Index Range for RDPMCProcessor FamilyCPUID Family/Model/Other SignaturesValid PMCIndex Range40-bitCountersP6Family 06H0, 10, 1Pentium® 4, Intel® XeonprocessorsFamily 0FH; Model 00H,01H, 02H≥ 0 and ≤ 17≥ 0 and ≤ 17Pentium 4, Intel Xeon processors(Family 0FH; Model03H, 04H, 06H) and (L3is absent)≥ 0 and ≤ 17≥ 0 and ≤ 17Pentium M processorsFamily 06H, Model 09H,0DH0, 10, 164-bit Intel Xeon processorswith L3(Family 0FH; Model03H, 04H) and (L3 ispresent)≥ 0 and ≤ 25≥ 0 and ≤ 174-246 Vol.
2BRDPMC—Read Performance-Monitoring CountersINSTRUCTION SET REFERENCE, N-ZTable 4-2. Valid Performance Counter Index Range for RDPMC (Contd.)Processor FamilyCPUID Family/Model/Other SignaturesValid PMCIndex Range40-bitCountersIntel® Core™ Solo and Intel®Core™ Duo processors, Dual-coreIntel® Xeon® processor LVFamily 06H, Model 0EH0, 10, 1Intel® Core™2 Duo processor,Intel Xeon processor 3000,5100, 5300 Series - generalpurpose PMCFamily 06H, Model 0FH0, 10, 1Intel Xeon processors 7100series with L3(Family 0FH; Model06H) and (L3 ispresent)≥ 0 and ≤ 25≥ 0 and ≤ 17The Pentium 4 and Intel Xeon processors also support “fast” (32-bit) and “slow”(40-bit) reads on the first 18 performance counters.
Selected this option usingECX[bit 31]. If bit 31 is set, RDPMC reads only the low 32 bits of the selected performance counter. If bit 31 is clear, all 40 bits are read. A 32-bit result is returned in EAXand EDX is set to 0. A 32-bit read executes faster on Pentium 4 processors and IntelXeon processors than a full 40-bit read.On 64-bit Intel Xeon processors with L3, performance counters with indices 18-25are 32-bit counters. EDX is cleared after executing RDPMC for these counters.
OnIntel Xeon processor 7100 series with L3, performance counters with indices 18-25are also 32-bit counters.In Intel Core 2 processor family, Intel Xeon processor 3000, 5100, and 5300 series,the fixed-function performance counters are 48-bits wide; they can be accessed byRDMPC with ECX between from 8000_0000H and 8000_0002H.When in protected or virtual 8086 mode, the performance-monitoring countersenabled (PCE) flag in register CR4 restricts the use of the RDPMC instruction asfollows.
When the PCE flag is set, the RDPMC instruction can be executed at any privilege level; when the flag is clear, the instruction can only be executed at privilegelevel 0. (When in real-address mode, the RDPMC instruction is always enabled.)The performance-monitoring counters can also be read with the RDMSR instruction,when executing at privilege level 0.The performance-monitoring counters are event counters that can be programmedto count events such as the number of instructions decoded, number of interruptsreceived, or number of cache loads.
Appendix A, “Performance Monitoring Events,” inthe Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B, liststhe events that can be counted for various processors in the Intel 64 and IA-32architecture families.The RDPMC instruction is not a serializing instruction; that is, it does not imply thatall the events caused by the preceding instructions have been completed or thatevents caused by subsequent instructions have not begun. If an exact event count isRDPMC—Read Performance-Monitoring CountersVol. 2B 4-247INSTRUCTION SET REFERENCE, N-Zdesired, software must insert a serializing instruction (such as the CPUID instruction)before and/or after the RDPCM instruction.In the Pentium 4 and Intel Xeon processors, performing back-to-back fast reads arenot guaranteed to be monotonic. To guarantee monotonicity on back-to-back reads,a serializing instruction must be placed between the two RDPMC instructions.The RDPMC instruction can execute in 16-bit addressing mode or virtual-8086 mode;however, the full contents of the ECX register are used to select the counter, and theevent count is stored in the full EAX and EDX registers.
The RDPMC instruction wasintroduced into the IA-32 Architecture in the Pentium Pro processor and the Pentiumprocessor with MMX technology. The earlier Pentium processors have performancemonitoring counters, but they must be read with the RDMSR instruction.Operation(* Intel Core 2 Duo processor family and Intel Xeon processor 3000, 5100, 5300 series*)IF (ECX = 0 or 1) and ((CR4.PCE = 1) or (CPL = 0) or (CR0.PE = 0))THEN IF (ECX[31] = 1)EAX ← IA32_FIXED_CTR(ECX)[30:0];EDX ← IA32_FIXED_CTR(ECX)[39:32];ELSE IF (ECX[30:0] in valid range)EAX ← PMC(ECX[30:0])[31:0];EDX ← PMC(ECX[30:0])[39:32];ELSE IF (ECX[31] and ECX[30:0] in valid fixed-counter range)EAX ← FIXED_PMC(ECX[30:0])[31:0];EDX ← FIXED_PMC(ECX[30:0])[47:32];ELSE (* ECX is not valid or CR4.PCE is 0 and CPL is 1, 2, or 3 and CR0.PE is 1 *)#GP(0);FI;(* P6 family processors and Pentium processor with MMX technology *)IF (ECX = 0 or 1) and ((CR4.PCE = 1) or (CPL = 0) or (CR0.PE = 0))THENEAX ← PMC(ECX)[31:0];EDX ← PMC(ECX)[39:32];ELSE (* ECX is not 0 or 1 or CR4.PCE is 0 and CPL is 1, 2, or 3 and CR0.PE is 1 *)#GP(0);FI;(* Processors with CPUID family 15 *)IF ((CR4.PCE = 1) or (CPL = 0) or (CR0.PE = 0))THEN IF (ECX[30:0] = 0:17)THEN IF ECX[31] = 0THENEAX ← PMC(ECX[30:0])[31:0]; (* 40-bit read *)4-248 Vol.
2BRDPMC—Read Performance-Monitoring CountersINSTRUCTION SET REFERENCE, N-ZEDX ← PMC(ECX[30:0])[39:32];ELSE (* ECX[31] = 1*)THENEAX ← PMC(ECX[30:0])[31:0]; (* 32-bit read *)EDX ← 0;FI;ELSE IF (*64-bit Intel Xeon processor with L3 *)THEN IF (ECX[30:0] = 18:25 )EAX ← PMC(ECX[30:0])[31:0]; (* 32-bit read *)EDX ← 0;FI;ELSE IF (*Intel Xeon processor 7100 series with L3 *)THEN IF (ECX[30:0] = 18:25 )EAX ← PMC(ECX[30:0])[31:0]; (* 32-bit read *)EDX ← 0;FI;ELSE (* Invalid PMC index in ECX[30:0], see Table 4-4.
*)GP(0);FI;ELSE (* CR4.PCE = 0 and (CPL = 1, 2, or 3) and CR0.PE = 1 *)#GP(0);FI;Flags AffectedNone.Protected Mode Exceptions#GP(0)If the current privilege level is not 0 and the PCE flag in the CR4register is clear.If an invalid performance counter index is specified (seeTable 4-2).(Pentium 4 and Intel Xeon processors) If the value in ECX[30:0]is not within the valid range.#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#GPIf an invalid performance counter index is specified (seeTable 4-2).(Pentium 4 and Intel Xeon processors) If the value in ECX[30:0]is not within the valid range.#UDIf the LOCK prefix is used.RDPMC—Read Performance-Monitoring CountersVol.
2B 4-249INSTRUCTION SET REFERENCE, N-ZVirtual-8086 Mode Exceptions#GP(0)If the PCE flag in the CR4 register is clear.If an invalid performance counter index is specified (seeTable 4-2).(Pentium 4 and Intel Xeon processors) If the value in ECX[30:0]is not within the valid range.#UDIf the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#GP(0)If the current privilege level is not 0 and the PCE flag in the CR4register is clear.If an invalid performance counter index is specified in ECX[30:0](see Table 4-2).#UD4-250 Vol. 2BIf the LOCK prefix is used.RDPMC—Read Performance-Monitoring CountersINSTRUCTION SET REFERENCE, N-ZRDTSC—Read Time-Stamp CounterOpcodeInstruction64-BitModeCompat/Leg ModeDescription0F 31RDTSCValidValidRead time-stamp counter intoEDX:EAX.DescriptionLoads the current value of the processor’s time-stamp counter (a 64-bit MSR) intothe EDX:EAX registers.
The EDX register is loaded with the high-order 32 bits of theMSR and the EAX register is loaded with the low-order 32 bits. (On processors thatsupport the Intel 64 architecture, the high-order 32 bits of each of RAX and RDX arecleared.)The processor monotonically increments the time-stamp counter MSR every clockcycle and resets it to 0 whenever the processor is reset.
See “Time Stamp Counter”in Chapter 18 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual,Volume 3B, for specific details of the time stamp counter behavior.When in protected or virtual 8086 mode, the time stamp disable (TSD) flag inregister CR4 restricts the use of the RDTSC instruction as follows. When the TSD flagis clear, the RDTSC instruction can be executed at any privilege level; when the flagis set, the instruction can only be executed at privilege level 0. (When in real-addressmode, the RDTSC instruction is always enabled.)The time-stamp counter can also be read with the RDMSR instruction, whenexecuting at privilege level 0.The RDTSC instruction is not a serializing instruction. Thus, it does not necessarilywait until all previous instructions have been executed before reading the counter.Similarly, subsequent instructions may begin execution before the read operation isperformed.This instruction was introduced by the Pentium processor.See “Changes to Instruction Behavior in VMX Non-Root Operation” in Chapter 21 ofthe Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B, formore information about the behavior of this instruction in VMX non-root operation.OperationIF (CR4.TSD = 0) or (CPL = 0) or (CR0.PE = 0)THEN EDX:EAX ← TimeStampCounter;ELSE (* CR4.TSD = 1 and (CPL = 1, 2, or 3) and CR0.PE = 1 *)#GP(0);FI;RDTSC—Read Time-Stamp CounterVol.
2B 4-251INSTRUCTION SET REFERENCE, N-ZFlags AffectedNone.Protected Mode Exceptions#GP(0)If the TSD flag in register CR4 is set and the CPL is greater than0.#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#UDIf the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)If the TSD flag in register CR4 is set.#UDIf the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode ExceptionsSame exceptions as in protected mode.4-252 Vol. 2BRDTSC—Read Time-Stamp CounterINSTRUCTION SET REFERENCE, N-ZREP/REPE/REPZ/REPNE/REPNZ—Repeat String Operation PrefixOpcodeInstruction64-BitModeCompat/Leg ModeDescriptionF3 6CREP INS m8, DXValidValidInput (E)CX bytes from port DXinto ES:[(E)DI].F3 6CREP INS m8, DXValidN.E.Input RCX bytes from port DXinto [RDI].F3 6DREP INS m16, DXValidValidInput (E)CX words from port DXinto ES:[(E)DI.]F3 6DREP INS m32, DXValidValidInput (E)CX doublewords fromport DX into ES:[(E)DI].F3 6DREP INS r/m32, DXValidN.E.Input RCX default size from portDX into [RDI].F3 A4REP MOVS m8, m8ValidValidMove (E)CX bytes fromDS:[(E)SI] to ES:[(E)DI].F3 REX.W A4REP MOVS m8, m8ValidN.E.Move RCX bytes from [RSI] to[RDI].F3 A5REP MOVS m16,m16ValidValidMove (E)CX words fromDS:[(E)SI] to ES:[(E)DI].F3 A5REP MOVS m32,m32ValidValidMove (E)CX doublewords fromDS:[(E)SI] to ES:[(E)DI].F3 REX.W A5REP MOVS m64,m64ValidN.E.Move RCX quadwords from [RSI]to [RDI].F3 6EREP OUTS DX, r/m8 ValidValidOutput (E)CX bytes fromDS:[(E)SI] to port DX.F3 REX.W 6EREP OUTS DX,r/m8*ValidN.E.Output RCX bytes from [RSI] toport DX.F3 6FREP OUTS DX,r/m16ValidValidOutput (E)CX words fromDS:[(E)SI] to port DX.F3 6FREP OUTS DX,r/m32ValidValidOutput (E)CX doublewords fromDS:[(E)SI] to port DX.F3 REX.W 6FREP OUTS DX,r/m32ValidN.E.Output RCX default size from[RSI] to port DX.F3 ACREP LODS ALValidValidLoad (E)CX bytes from DS:[(E)SI]to AL.F3 REX.W ACREP LODS ALValidN.E.Load RCX bytes from [RSI] toAL.F3 ADREP LODS AXValidValidLoad (E)CX words from DS:[(E)SI]to AX.REP/REPE/REPZ/REPNE/REPNZ—Repeat String Operation PrefixVol.
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