Volume 2B Instruction Set Reference N-Z (794102), страница 34
Текст из файла (страница 34)
2B 4-237INSTRUCTION SET REFERENCE, N-ZRCPPS—Compute Reciprocals of Packed Single-Precision FloatingPoint ValuesOpcodeInstruction64-BitModeCompat/Leg ModeDescription0F 53 /rRCPPS xmm1,xmm2/m128ValidValidComputes the approximate reciprocalsof the packed single-precision floatingpoint values in xmm2/m128 and storesthe results in xmm1.DescriptionPerforms a SIMD computation of the approximate reciprocals of the four packedsingle-precision floating-point values in the source operand (second operand) storesthe packed single-precision floating-point results in the destination operand. Thesource operand can be an XMM register or a 128-bit memory location.
The destination operand is an XMM register. See Figure 10-5 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for an illustration of a SIMD singleprecision floating-point operation.The relative error for this approximation is:|Relative Error| ≤ 1.5 ∗ 2−12The RCPPS instruction is not affected by the rounding control bits in the MXCSRregister.
When a source value is a 0.0, an ∞ of the sign of the source value isreturned. A denormal source value is treated as a 0.0 (of the same sign). Tiny resultsare always flushed to 0.0, with the sign of the operand. (Input values greater than orequal to |1.11111111110100000000000B∗2125| are guaranteed to not produce tinyresults; input values less than or equal to |1.00000000000110000000001B*2126|are guaranteed to produce tiny results, which are in turn flushed to 0.0; and inputvalues in between this range may or may not produce tiny results, depending on theimplementation.) When a source value is an SNaN or QNaN, the SNaN is converted toa QNaN or the source QNaN is returned.In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction toaccess additional registers (XMM8-XMM15).OperationDEST[31:0] ← APPROXIMATE(1.0/(SRC[31:0]));DEST[63:32] ← APPROXIMATE(1.0/(SRC[63:32]));DEST[95:64] ← APPROXIMATE(1.0/(SRC[95:64]));DEST[127:96] ← APPROXIMATE(1.0/(SRC[127:96]));Intel C/C++ Compiler Intrinsic EquivalentRCCPS__m128 _mm_rcp_ps(__m128 a)4-238 Vol.
2BRCPPS—Compute Reciprocals of Packed Single-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, N-ZSIMD Floating-Point ExceptionsNone.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.Real-Address Mode Exceptions#GP(0)If a memory operand is not aligned on a 16-byte boundary,regardless of segment.If any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.RCPPS—Compute Reciprocals of Packed Single-Precision Floating-Point ValuesVol.
2B 4-239INSTRUCTION SET REFERENCE, N-ZIf memory operand is not aligned on a 16-byte boundary,regardless of segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.4-240 Vol. 2BRCPPS—Compute Reciprocals of Packed Single-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, N-ZRCPSS—Compute Reciprocal of Scalar Single-Precision Floating-PointValuesOpcodeInstruction64-BitModeCompat/Leg ModeDescriptionValidValidComputes the approximate reciprocal ofthe scalar single-precision floating-pointvalue in xmm2/m32 and stores the resultin xmm1.F3 0F 53 RCPSS xmm1,/rxmm2/m32DescriptionComputes of an approximate reciprocal of the low single-precision floating-pointvalue in the source operand (second operand) and stores the single-precisionfloating-point result in the destination operand.
The source operand can be an XMMregister or a 32-bit memory location. The destination operand is an XMM register.The three high-order doublewords of the destination operand remain unchanged.See Figure 10-6 in the Intel® 64 and IA-32 Architectures Software Developer’sManual, Volume 1, for an illustration of a scalar single-precision floating-point operation.The relative error for this approximation is:|Relative Error| ≤ 1.5 ∗ 2−12The RCPSS instruction is not affected by the rounding control bits in the MXCSRregister. When a source value is a 0.0, an ∞ of the sign of the source value isreturned. A denormal source value is treated as a 0.0 (of the same sign). Tiny resultsare always flushed to 0.0, with the sign of the operand.
(Input values greater than orequal to |1.11111111110100000000000B∗2125| are guaranteed to not produce tinyresults; input values less than or equal to |1.00000000000110000000001B*2126|are guaranteed to produce tiny results, which are in turn flushed to 0.0; and inputvalues in between this range may or may not produce tiny results, depending on theimplementation.) When a source value is an SNaN or QNaN, the SNaN is converted toa QNaN or the source QNaN is returned.In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction toaccess additional registers (XMM8-XMM15).OperationDEST[31:0] ← APPROX (1.0/(SRC[31:0]));(* DEST[127:32] unchanged *)Intel C/C++ Compiler Intrinsic EquivalentRCPSS__m128 _mm_rcp_ss(__m128 a)RCPSS—Compute Reciprocal of Scalar Single-Precision Floating-Point ValuesVol.
2B 4-241INSTRUCTION SET REFERENCE, N-ZSIMD Floating-Point ExceptionsNone.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.Real-Address Mode ExceptionsGP(0)If any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.#AC(0)For unaligned memory reference.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.4-242 Vol.
2BRCPSS—Compute Reciprocal of Scalar Single-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, N-Z#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.RCPSS—Compute Reciprocal of Scalar Single-Precision Floating-Point ValuesVol. 2B 4-243INSTRUCTION SET REFERENCE, N-ZRDMSR—Read from Model Specific RegisterOpcode*Instruction64-BitModeCompat/Leg ModeDescription0F 32RDMSRValidValidLoad MSR specified by ECX intoEDX:EAX.NOTES:* See IA-32 Architecture Compatibility section below.DescriptionLoads the contents of a 64-bit model specific register (MSR) specified in the ECXregister into registers EDX:EAX.
(On processors that support the Intel 64 architecture, the high-order 32 bits of RCX are ignored.) The EDX register is loaded with thehigh-order 32 bits of the MSR and the EAX register is loaded with the low-order 32bits. (On processors that support the Intel 64 architecture, the high-order 32 bits ofeach of RAX and RDX are cleared.) If fewer than 64 bits are implemented in the MSRbeing read, the values returned to EDX:EAX in unimplemented bit locations areundefined.This instruction must be executed at privilege level 0 or in real-address mode; otherwise, a general protection exception #GP(0) will be generated.
Specifying a reservedor unimplemented MSR address in ECX will also cause a general protection exception.The MSRs control functions for testability, execution tracing, performance-monitoring, and machine check errors. Appendix B, “Model-Specific Registers (MSRs),” inthe Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B, listsall the MSRs that can be read with this instruction and their addresses. Note thateach processor family has its own set of MSRs.The CPUID instruction should be used to determine whether MSRs are supported(CPUID.01H:EDX[5] = 1) before using this instruction.IA-32 Architecture CompatibilityThe MSRs and the ability to read them with the RDMSR instruction were introducedinto the IA-32 Architecture with the Pentium processor.
Execution of this instructionby an IA-32 processor earlier than the Pentium processor results in an invalid opcodeexception #UD.See “Changes to Instruction Behavior in VMX Non-Root Operation” in Chapter 21 ofthe Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B, formore information about the behavior of this instruction in VMX non-root operation.OperationEDX:EAX ← MSR[ECX];4-244 Vol.
2BRDMSR—Read from Model Specific RegisterINSTRUCTION SET REFERENCE, N-ZFlags AffectedNone.Protected Mode Exceptions#GP(0)If the current privilege level is not 0.If the value in ECX specifies a reserved or unimplemented MSRaddress.#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#GPIf the value in ECX specifies a reserved or unimplemented MSRaddress.#UDIf the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)The RDMSR instruction is not recognized in virtual-8086 mode.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#GP(0)If the current privilege level is not 0.If the value in ECX or RCX specifies a reserved or unimplemented MSR address.#UDIf the LOCK prefix is used.RDMSR—Read from Model Specific RegisterVol.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
