Volume 2B Instruction Set Reference N-Z (794102), страница 26
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2B 4-183INSTRUCTION SET REFERENCE, N-Z(128-bit operations only) If memory operand is not aligned on a16-byte boundary, regardless of segment.#UDIf CR0.EM[bit 2] = 1.(128-bit operations only) If CR4.OSFXSR[bit 9] = 0.(128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made while the current privilegelevel is 3.4-184 Vol. 2BPSRAW/PSRAD—Shift Packed Data Right ArithmeticINSTRUCTION SET REFERENCE, N-ZPSRLDQ—Shift Double Quadword Right LogicalOpcodeInstruction64-BitModeCompat/Leg ModeDescription66 0F 73 /3 ibPSRLDQ xmm1,imm8ValidValidShift xmm1 right by imm8 whileshifting in 0s.DescriptionShifts the destination operand (first operand) to the right by the number of bytesspecified in the count operand (second operand).
The empty high-order bytes arecleared (set to all 0s). If the value specified by the count operand is greater than 15,the destination operand is set to all 0s. The destination operand is an XMM register.The count operand is an 8-bit immediate.In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction toaccess additional registers (XMM8-XMM15).OperationTEMP ← COUNT;IF (TEMP > 15) THEN TEMP ← 16; FI;DEST ← DEST >> (temp ∗ 8);Intel C/C++ Compiler Intrinsic EquivalentsPSRLDQ__m128i _mm_srli_si128 ( __m128i a, int imm)Flags AffectedNone.Numeric ExceptionsNone.Protected Mode Exceptions#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.Real-Address Mode ExceptionsSame exceptions as in protected mode.PSRLDQ—Shift Double Quadword Right LogicalVol.
2B 4-185INSTRUCTION SET REFERENCE, N-ZVirtual-8086 Mode ExceptionsSame exceptions as in protected mode.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode ExceptionsSame exceptions as in protected mode.Numeric ExceptionsNone.4-186 Vol. 2BPSRLDQ—Shift Double Quadword Right LogicalINSTRUCTION SET REFERENCE, N-ZPSRLW/PSRLD/PSRLQ—Shift Packed Data Right LogicalOpcodeInstruction64-BitModeCompat/Leg ModeDescription0F D1 /rPSRLW mm,mm/m64ValidValidShift words in mm right by amountspecified in mm/m64 while shifting in0s.66 0F D1 /rPSRLW xmm1,xmm2/m128ValidValidShift words in xmm1 right by amountspecified in xmm2/m128 whileshifting in 0s.0F 71 /2 ibPSRLW mm,imm8ValidValidShift words in mm right by imm8 whileshifting in 0s.66 0F 71 /2 ib PSRLW xmm1,imm8ValidValidShift words in xmm1 right by imm8while shifting in 0s.0F D2 /rPSRLD mm,mm/m64ValidValidShift doublewords in mm right byamount specified in mm/m64 whileshifting in 0s.66 0F D2 /rPSRLD xmm1,xmm2/m128ValidValidShift doublewords in xmm1 right byamount specified in xmm2 /m128while shifting in 0s.0F 72 /2 ibPSRLD mm,imm8ValidValidShift doublewords in mm right byimm8 while shifting in 0s.66 0F 72 /2 ib PSRLD xmm1,imm8ValidValidShift doublewords in xmm1 right byimm8 while shifting in 0s.0F D3 /rPSRLQ mm,mm/m64ValidValidShift mm right by amount specified inmm/m64 while shifting in 0s.66 0F D3 /rPSRLQ xmm1,xmm2/m128ValidValidShift quadwords in xmm1 right byamount specified in xmm2/m128while shifting in 0s.0F 73 /2 ibPSRLQ mm,imm8ValidValidShift mm right by imm8 while shiftingin 0s.ValidValidShift quadwords in xmm1 right byimm8 while shifting in 0s.66 0F 73 /2 ib PSRLQ xmm1,imm8DescriptionShifts the bits in the individual data elements (words, doublewords, or quadword) inthe destination operand (first operand) to the right by the number of bits specified inthe count operand (second operand).
As the bits in the data elements are shiftedright, the empty high-order bits are cleared (set to 0). If the value specified by thecount operand is greater than 15 (for words), 31 (for doublewords), or 63 (for aPSRLW/PSRLD/PSRLQ—Shift Packed Data Right LogicalVol. 2B 4-187INSTRUCTION SET REFERENCE, N-Zquadword), then the destination operand is set to all 0s. Figure 4-10 gives anexample of shifting words in a 64-bit operand.The destination operand may be an MMX technology register or an XMM register; thecount operand can be either an MMX technology register or an 64-bit memory location, an XMM register or a 128-bit memory location, or an 8-bit immediate. Note thatonly the first 64-bits of a 128-bit count operand are checked to compute the count.Pre-ShiftDESTX3X2X1X3 >> COUNTX2 >> COUNTX0Shift Rightwith ZeroExtensionPost-ShiftDESTX1 >> COUNT X0 >> COUNTFigure 4-10.
PSRLW, PSRLD, and PSRLQ Instruction Operation Using 64-bit OperandThe PSRLW instruction shifts each of the words in the destination operand to the rightby the number of bits specified in the count operand; the PSRLD instruction shiftseach of the doublewords in the destination operand; and the PSRLQ instruction shiftsthe quadword (or quadwords) in the destination operand.In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction toaccess additional registers (XMM8-XMM15).OperationPSRLW instruction with 64-bit operand:IF (COUNT > 15)THENDEST[64:0] ← 0000000000000000HELSEDEST[15:0] ← ZeroExtend(DEST[15:0] >> COUNT);(* Repeat shift operation for 2nd and 3rd words *)DEST[63:48] ← ZeroExtend(DEST[63:48] >> COUNT);FI;PSRLD instruction with 64-bit operand:IF (COUNT > 31)THENDEST[64:0] ← 0000000000000000HELSEDEST[31:0] ← ZeroExtend(DEST[31:0] >> COUNT);DEST[63:32] ← ZeroExtend(DEST[63:32] >> COUNT);FI;4-188 Vol.
2BPSRLW/PSRLD/PSRLQ—Shift Packed Data Right LogicalINSTRUCTION SET REFERENCE, N-ZPSRLQ instruction with 64-bit operand:IF (COUNT > 63)THENDEST[64:0] ← 0000000000000000HELSEDEST ← ZeroExtend(DEST >> COUNT);FI;PSRLW instruction with 128-bit operand:COUNT ← COUNT_SOURCE[63:0];IF (COUNT > 15)THENDEST[128:0] ← 00000000000000000000000000000000HELSEDEST[15:0] ← ZeroExtend(DEST[15:0] >> COUNT);(* Repeat shift operation for 2nd through 7th words *)DEST[127:112] ← ZeroExtend(DEST[127:112] >> COUNT);FI;PSRLD instruction with 128-bit operand:COUNT ← COUNT_SOURCE[63:0];IF (COUNT > 31)THENDEST[128:0] ← 00000000000000000000000000000000HELSEDEST[31:0] ← ZeroExtend(DEST[31:0] >> COUNT);(* Repeat shift operation for 2nd and 3rd doublewords *)DEST[127:96] ← ZeroExtend(DEST[127:96] >> COUNT);FI;PSRLQ instruction with 128-bit operand:COUNT ← COUNT_SOURCE[63:0];IF (COUNT > 15)THENDEST[128:0] ← 00000000000000000000000000000000HELSEDEST[63:0] ← ZeroExtend(DEST[63:0] >> COUNT);DEST[127:64] ← ZeroExtend(DEST[127:64] >> COUNT);FI;Intel C/C++ Compiler Intrinsic EquivalentsPSRLW__m64 _mm_srli_pi16(__m64 m, int count)PSRLW__m64 _mm_srl_pi16 (__m64 m, __m64 count)PSRLW/PSRLD/PSRLQ—Shift Packed Data Right LogicalVol.
2B 4-189INSTRUCTION SET REFERENCE, N-ZPSRLW__m128i _mm_srli_epi16 (__m128i m, int count)PSRLW__m128i _mm_srl_epi16 (__m128i m, __m128i count)PSRLD__m64 _mm_srli_pi32 (__m64 m, int count)PSRLD__m64 _mm_srl_pi32 (__m64 m, __m64 count)PSRLD__m128i _mm_srli_epi32 (__m128i m, int count)PSRLD__m128i _mm_srl_epi32 (__m128i m, __m128i count)PSRLQ__m64 _mm_srli_si64 (__m64 m, int count)PSRLQ__m64 _mm_srl_si64 (__m64 m, __m64 count)PSRLQ__m128i _mm_srli_epi64 (__m128i m, int count)PSRLQ__m128i _mm_srl_epi64 (__m128i m, __m128i count)Flags AffectedNone.Numeric ExceptionsNone.Protected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.(128-bit operations only) If a memory operand is not aligned ona 16-byte boundary, regardless of segment.#SS(0)If a memory operand effective address is outside the SSsegment limit.#UDIf CR0.EM[bit 2] = 1.(128-bit operations only) If CR4.OSFXSR[bit 9] = 0.(128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made while the current privilegelevel is 3.Real-Address Mode Exceptions#GP(0)4-190 Vol.
2B(128-bit operations only) If a memory operand is not aligned ona 16-byte boundary, regardless of segment.PSRLW/PSRLD/PSRLQ—Shift Packed Data Right LogicalINSTRUCTION SET REFERENCE, N-ZIf any part of the operand lies outside of the effective addressspace from 0 to FFFFH.#UDIf CR0.EM[bit 2] = 1.(128-bit operations only) If CR4.OSFXSR[bit 9] = 0.(128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made.Compatibility Mode ExceptionsSame as for protected mode exceptions.#SS(0)If a memory address referencing the SS segment is in a noncanonical form.64-Bit Mode Exceptions#GP(0)If the memory address is in a non-canonical form.(128-bit operations only) If memory operand is not aligned on a16-byte boundary, regardless of segment.#UDIf CR0.EM[bit 2] = 1.(128-bit operations only) If CR4.OSFXSR[bit 9] = 0.(128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made while the current privilegelevel is 3.PSRLW/PSRLD/PSRLQ—Shift Packed Data Right LogicalVol.
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