Volume 2B Instruction Set Reference N-Z (794102), страница 25
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Figure 4-8 gives an example ofshifting words in a 64-bit operand.The destination operand may be an MMX technology register or an XMM register; thecount operand can be either an MMX technology register or an 64-bit memory loca-PSLLW/PSLLD/PSLLQ—Shift Packed Data Left LogicalVol. 2B 4-175INSTRUCTION SET REFERENCE, N-Ztion, an XMM register or a 128-bit memory location, or an 8-bit immediate. Note thatonly the first 64-bits of a 128-bit count operand are checked to compute the count.Pre-ShiftDESTX3X2X1X3 << COUNTX2 << COUNTX0Shift Leftwith ZeroExtensionPost-ShiftDESTX1 << COUNT X0 << COUNTFigure 4-8. PSLLW, PSLLD, and PSLLQ Instruction Operation Using 64-bit OperandThe PSLLW instruction shifts each of the words in the destination operand to the leftby the number of bits specified in the count operand; the PSLLD instruction shiftseach of the doublewords in the destination operand; and the PSLLQ instruction shiftsthe quadword (or quadwords) in the destination operand.In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction toaccess additional registers (XMM8-XMM15).OperationPSLLW instruction with 64-bit operand:IF (COUNT > 15)THENDEST[64:0] ← 0000000000000000H;ELSEDEST[15:0] ← ZeroExtend(DEST[15:0] << COUNT);(* Repeat shift operation for 2nd and 3rd words *)DEST[63:48] ← ZeroExtend(DEST[63:48] << COUNT);FI;PSLLD instruction with 64-bit operand:IF (COUNT > 31)THENDEST[64:0] ← 0000000000000000H;ELSEDEST[31:0] ← ZeroExtend(DEST[31:0] << COUNT);DEST[63:32] ← ZeroExtend(DEST[63:32] << COUNT);FI;PSLLQ instruction with 64-bit operand:IF (COUNT > 63)THEN4-176 Vol.
2BPSLLW/PSLLD/PSLLQ—Shift Packed Data Left LogicalINSTRUCTION SET REFERENCE, N-ZDEST[64:0] ← 0000000000000000H;ELSEDEST ← ZeroExtend(DEST << COUNT);FI;PSLLW instruction with 128-bit operand:COUNT ← COUNT_SOURCE[63:0];IF (COUNT > 15)THENDEST[128:0] ← 00000000000000000000000000000000H;ELSEDEST[15:0] ← ZeroExtend(DEST[15:0] << COUNT);(* Repeat shift operation for 2nd through 7th words *)DEST[127:112] ← ZeroExtend(DEST[127:112] << COUNT);FI;PSLLD instruction with 128-bit operand:COUNT ← COUNT_SOURCE[63:0];IF (COUNT > 31)THENDEST[128:0] ← 00000000000000000000000000000000H;ELSEDEST[31:0] ← ZeroExtend(DEST[31:0] << COUNT);(* Repeat shift operation for 2nd and 3rd doublewords *)DEST[127:96] ← ZeroExtend(DEST[127:96] << COUNT);FI;PSLLQ instruction with 128-bit operand:COUNT ← COUNT_SOURCE[63:0];IF (COUNT > 63)THENDEST[128:0] ← 00000000000000000000000000000000H;ELSEDEST[63:0] ← ZeroExtend(DEST[63:0] << COUNT);DEST[127:64] ← ZeroExtend(DEST[127:64] << COUNT);FI;Intel C/C++ Compiler Intrinsic EquivalentsPSLLW__m64 _mm_slli_pi16 (__m64 m, int count)PSLLW__m64 _mm_sll_pi16(__m64 m, __m64 count)PSLLW__m128i _mm_slli_pi16(__m64 m, int count)PSLLW__m128i _mm_slli_pi16(__m128i m, __m128i count)PSLLD__m64 _mm_slli_pi32(__m64 m, int count)PSLLW/PSLLD/PSLLQ—Shift Packed Data Left LogicalVol.
2B 4-177INSTRUCTION SET REFERENCE, N-ZPSLLD__m64 _mm_sll_pi32(__m64 m, __m64 count)PSLLD__m128i _mm_slli_epi32(__m128i m, int count)PSLLD__m128i _mm_sll_epi32(__m128i m, __m128i count)PSLLQ__m64 _mm_slli_si64(__m64 m, int count)PSLLQ__m64 _mm_sll_si64(__m64 m, __m64 count)PSLLQ__m128i _mm_slli_si64(__m128i m, int count)PSLLQ__m128i _mm_sll_si64(__m128i m, __m128i count)Flags AffectedNone.Numeric ExceptionsNone.Protected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.(128-bit operations only) If a memory operand is not aligned ona 16-byte boundary, regardless of segment.#SS(0)If a memory operand effective address is outside the SSsegment limit.#UDIf CR0.EM[bit 2] = 1.(128-bit operations only) If CR4.OSFXSR[bit 9] = 0.(128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made while the current privilegelevel is 3.Real-Address Mode Exceptions#GP(0)(128-bit operations only) If a memory operand is not aligned ona 16-byte boundary, regardless of segment.If any part of the operand lies outside of the effective addressspace from 0 to FFFFH.#UDIf CR0.EM[bit 2] = 1.(128-bit operations only) If CR4.OSFXSR[bit 9] = 0.4-178 Vol.
2BPSLLW/PSLLD/PSLLQ—Shift Packed Data Left LogicalINSTRUCTION SET REFERENCE, N-Z(128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made.Compatibility Mode ExceptionsSame as for protected mode exceptions.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.(128-bit operations only) If memory operand is not aligned on a16-byte boundary, regardless of segment.#UDIf CR0.EM[bit 2] = 1.(128-bit operations only) If CR4.OSFXSR[bit 9] = 0.(128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made while the current privilegelevel is 3.PSLLW/PSLLD/PSLLQ—Shift Packed Data Left LogicalVol.
2B 4-179INSTRUCTION SET REFERENCE, N-ZPSRAW/PSRAD—Shift Packed Data Right ArithmeticOpcodeInstruction64-BitModeCompat/Leg ModeDescription0F E1 /rPSRAW mm,mm/m64ValidValidShift words in mm right bymm/m64 while shifting in signbits.66 0F E1 /rPSRAW xmm1,xmm2/m128ValidValidShift words in xmm1 right byxmm2/m128 while shifting in signbits.0F 71 /4 ibPSRAW mm, imm8 ValidValidShift words in mm right by imm8while shifting in sign bits66 0F 71 /4 ibPSRAW xmm1,imm8ValidValidShift words in xmm1 right byimm8 while shifting in sign bits0F E2 /rPSRAD mm,mm/m64ValidValidShift doublewords in mm right bymm/m64 while shifting in signbits.66 0F E2 /rPSRAD xmm1,xmm2/m128ValidValidShift doubleword in xmm1 rightby xmm2 /m128 while shifting insign bits.0F 72 /4 ibPSRAD mm, imm8 ValidValidShift doublewords in mm right byimm8 while shifting in sign bits.66 0F 72 /4 ibPSRAD xmm1,imm8ValidShift doublewords in xmm1 rightby imm8 while shifting in sign bits.ValidDescriptionShifts the bits in the individual data elements (words or doublewords) in the destination operand (first operand) to the right by the number of bits specified in the countoperand (second operand).
As the bits in the data elements are shifted right, theempty high-order bits are filled with the initial value of the sign bit of the dataelement. If the value specified by the count operand is greater than 15 (for words) or31 (for doublewords), each destination data element is filled with the initial value ofthe sign bit of the element. (Figure 4-9 gives an example of shifting words in a 64-bitoperand.)4-180 Vol. 2BPSRAW/PSRAD—Shift Packed Data Right ArithmeticINSTRUCTION SET REFERENCE, N-ZPre-ShiftDESTX3X2X3 >> COUNTX2 >> COUNTX1X0Shift Rightwith SignExtensionPost-ShiftDESTX1 >> COUNT X0 >> COUNTFigure 4-9.
PSRAW and PSRAD Instruction Operation Using a 64-bit OperandThe destination operand may be an MMX technology register or an XMM register; thecount operand can be either an MMX technology register or an 64-bit memory location, an XMM register or a 128-bit memory location, or an 8-bit immediate. Note thatonly the first 64-bits of a 128-bit count operand are checked to compute the count.The PSRAW instruction shifts each of the words in the destination operand to theright by the number of bits specified in the count operand, and the PSRAD instructionshifts each of the doublewords in the destination operand.In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction toaccess additional registers (XMM8-XMM15).OperationPSRAW instruction with 64-bit operand:IF (COUNT > 15)THEN COUNT ← 16;FI;DEST[15:0] ← SignExtend(DEST[15:0] >> COUNT);(* Repeat shift operation for 2nd and 3rd words *)DEST[63:48] ← SignExtend(DEST[63:48] >> COUNT);PSRAD instruction with 64-bit operand:IF (COUNT > 31)THEN COUNT ← 32;FI;DEST[31:0] ← SignExtend(DEST[31:0] >> COUNT);DEST[63:32] ← SignExtend(DEST[63:32] >> COUNT);PSRAW instruction with 128-bit operand:COUNT ← COUNT_SOURCE[63:0];PSRAW/PSRAD—Shift Packed Data Right ArithmeticVol.
2B 4-181INSTRUCTION SET REFERENCE, N-ZIF (COUNT > 15)THEN COUNT ← 16;FI;DEST[15:0] ← SignExtend(DEST[15:0] >> COUNT);(* Repeat shift operation for 2nd through 7th words *)DEST[127:112] ← SignExtend(DEST[127:112] >> COUNT);PSRAD instruction with 128-bit operand:COUNT ← COUNT_SOURCE[63:0];IF (COUNT > 31)THEN COUNT ← 32;FI;DEST[31:0] ← SignExtend(DEST[31:0] >> COUNT);(* Repeat shift operation for 2nd and 3rd doublewords *)DEST[127:96] ← SignExtend(DEST[127:96] >>COUNT);Intel C/C++ Compiler Intrinsic EquivalentsPSRAW__m64 _mm_srai_pi16 (__m64 m, int count)PSRAW__m64 _mm_sraw_pi16 (__m64 m, __m64 count)PSRAD__m64 _mm_srai_pi32 (__m64 m, int count)PSRAD__m64 _mm_sra_pi32 (__m64 m, __m64 count)PSRAW__m128i _mm_srai_epi16(__m128i m, int count)PSRAW__m128i _mm_sra_epi16(__m128i m, __m128i count))PSRAD__m128i _mm_srai_epi32 (__m128i m, int count)PSRAD__m128i _mm_sra_epi32 (__m128i m, __m128i count)Flags AffectedNone.Numeric ExceptionsNone.Protected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.(128-bit operations only) If a memory operand is not aligned ona 16-byte boundary, regardless of segment.4-182 Vol.
2BPSRAW/PSRAD—Shift Packed Data Right ArithmeticINSTRUCTION SET REFERENCE, N-Z#SS(0)#UDIf a memory operand effective address is outside the SSsegment limit.If CR0.EM[bit 2] = 1.(128-bit operations only) If CR4.OSFXSR[bit 9] = 0.(128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made while the current privilegelevel is 3.Real-Address Mode Exceptions#GP(0)(128-bit operations only) If a memory operand is not aligned ona 16-byte boundary, regardless of segment.If any part of the operand lies outside of the effective addressspace from 0 to FFFFH.#UDIf CR0.EM[bit 2] = 1.(128-bit operations only) If CR4.OSFXSR[bit 9] = 0.(128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made.Compatibility Mode ExceptionsSame as for protected mode exceptions.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.PSRAW/PSRAD—Shift Packed Data Right ArithmeticVol.
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