Volume 2B Instruction Set Reference N-Z (794102), страница 23
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The binaryencodings of the order operand fields select words (0, 1, 2 or 3, 4) from the highquadword of the source operand to be copied to the destination operand. The lowquadword of the source operand is copied to the low quadword of the destinationoperand.The source operand can be an XMM register or a 128-bit memory location. The destination operand is an XMM register.
The order operand is an 8-bit immediate. Notethat this instruction permits a word in the high quadword of the source operand to becopied to more than one word location in the high quadword of the destinationoperand.In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction toaccess additional registers (XMM8-XMM15).OperationDEST[63:0] ← SRC[63:0];DEST[79:64] ← (SRC >> (ORDER[1:0] ∗ 16))[79:64];DEST[95:80] ← (SRC >> (ORDER[3:2] ∗ 16))[79:64];DEST[111:96] ← (SRC >> (ORDER[5:4] ∗ 16))[79:64];DEST[127:112] ← (SRC >> (ORDER[7:6] ∗ 16))[79:64];Intel C/C++ Compiler Intrinsic EquivalentPSHUFHW__m128i _mm_shufflehi_epi16(__m128i a, int n)Flags AffectedNone.PSHUFHW—Shuffle Packed High WordsVol. 2B 4-159INSTRUCTION SET REFERENCE, N-ZNumeric ExceptionsNone.Protected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.#SS(0)#UDIf a memory operand effective address is outside the SSsegment limit.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#PF(fault-code)If a page fault occurs.Real-Address Mode Exceptions#GP(0)If a memory operand is not aligned on a 16-byte boundary,regardless of segment.If any part of the operand lies outside of the effective addressspace from 0 to FFFFH.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.Compatibility Mode ExceptionsSame as for protected mode exceptions.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.4-160 Vol.
2BPSHUFHW—Shuffle Packed High WordsINSTRUCTION SET REFERENCE, N-ZIf memory operand is not aligned on a 16-byte boundary,regardless of segment.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#PF(fault-code)If a page fault occurs.PSHUFHW—Shuffle Packed High WordsVol. 2B 4-161INSTRUCTION SET REFERENCE, N-ZPSHUFLW—Shuffle Packed Low WordsOpcodeInstruction64-BitModeCompat/Leg ModeDescriptionF2 0F 70 /r ibPSHUFLW xmm1,xmm2/m128, imm8ValidValidShuffle the low words inxmm2/m128 based on theencoding in imm8 and store theresult in xmm1.DescriptionCopies words from the low quadword of the source operand (second operand) andinserts them in the low quadword of the destination operand (first operand) at wordlocations selected with the order operand (third operand). This operation is similar tothe operation used by the PSHUFD instruction, which is illustrated in Figure 4-7.
Forthe PSHUFLW instruction, each 2-bit field in the order operand selects the contents ofone word location in the low quadword of the destination operand. The binary encodings of the order operand fields select words (0, 1, 2, or 3) from the low quadword ofthe source operand to be copied to the destination operand. The high quadword ofthe source operand is copied to the high quadword of the destination operand.The source operand can be an XMM register or a 128-bit memory location. The destination operand is an XMM register.
The order operand is an 8-bit immediate. Notethat this instruction permits a word in the low quadword of the source operand to becopied to more than one word location in the low quadword of the destinationoperand.In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction toaccess additional registers (XMM8-XMM15).OperationDEST[15:0] ← (SRC >> (ORDER[1:0] ∗ 16))[15:0];DEST[31:16] ← (SRC >> (ORDER[3:2] ∗ 16))[15:0];DEST[47:32] ← (SRC >> (ORDER[5:4] ∗ 16))[15:0];DEST[63:48] ← (SRC >> (ORDER[7:6] ∗ 16))[15:0];DEST[127:64] ← SRC[127:64];Intel C/C++ Compiler Intrinsic EquivalentPSHUFLW__m128i _mm_shufflelo_epi16(__m128i a, int n)Flags AffectedNone.4-162 Vol. 2BPSHUFLW—Shuffle Packed Low WordsINSTRUCTION SET REFERENCE, N-ZNumeric ExceptionsNone.Protected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.#SS(0)#UDIf a memory operand effective address is outside the SSsegment limit.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#PF(fault-code)If a page fault occurs.Real-Address Mode Exceptions#GP(0)If a memory operand is not aligned on a 16-byte boundary,regardless of segment.If any part of the operand lies outside of the effective addressspace from 0 to FFFFH.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.Compatibility Mode ExceptionsSame as for protected mode exceptions.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.PSHUFLW—Shuffle Packed Low WordsVol.
2B 4-163INSTRUCTION SET REFERENCE, N-ZIf memory operand is not aligned on a 16-byte boundary,regardless of segment.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#PF(fault-code)If a page fault occurs.4-164 Vol. 2BPSHUFLW—Shuffle Packed Low WordsINSTRUCTION SET REFERENCE, N-ZPSHUFW—Shuffle Packed WordsOpcodeInstruction64-BitModeCompat/Leg ModeDescription0F 70 /r ibPSHUFW mm1,mm2/m64, imm8ValidValidShuffle the words in mm2/m64based on the encoding in imm8 andstore the result in mm1.DescriptionCopies words from the source operand (second operand) and inserts them in thedestination operand (first operand) at word locations selected with the order operand(third operand).
This operation is similar to the operation used by the PSHUFDinstruction, which is illustrated in Figure 4-7. For the PSHUFW instruction, each 2-bitfield in the order operand selects the contents of one word location in the destinationoperand. The encodings of the order operand fields select words from the sourceoperand to be copied to the destination operand.The source operand can be an MMX technology register or a 64-bit memory location.The destination operand is an MMX technology register. The order operand is an 8-bitimmediate. Note that this instruction permits a word in the source operand to becopied to more than one word location in the destination operand.In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction toaccess additional registers (XMM8-XMM15).OperationDEST[15:0] ← (SRC >> (ORDER[1:0] * 16))[15:0];DEST[31:16] ← (SRC >> (ORDER[3:2] * 16))[15:0];DEST[47:32] ← (SRC >> (ORDER[5:4] * 16))[15:0];DEST[63:48] ← (SRC >> (ORDER[7:6] * 16))[15:0];Intel C/C++ Compiler Intrinsic EquivalentPSHUFW__m64 _mm_shuffle_pi16(__m64 a, int n)Flags AffectedNone.Numeric ExceptionsNone.PSHUFW—Shuffle Packed WordsVol.
2B 4-165INSTRUCTION SET REFERENCE, N-ZProtected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.#UDIf CR0.EM[bit 2] = 1.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.Real-Address Mode Exceptions#GP(0)If any part of the operand lies outside of the effective addressspace from 0 to FFFFH.#UDIf CR0.EM[bit 2] = 1.#NMIf CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.Compatibility Mode ExceptionsSame as for protected mode exceptions.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#UDIf CR0.EM[bit 2] = 1.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.4-166 Vol.
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