Volume 2B Instruction Set Reference N-Z (794102), страница 20
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(The D flag in the current code segment’ssegment descriptor determines the operand-size attribute.)This instruction executes as described in non-64-bit modes. It is not valid in 64-bitmode.OperationIF 64-Bit ModeTHEN#UD;ELSEIF OperandSize = 32 (* Instruction = POPAD *)THENEDI ← Pop();ESI ← Pop();EBP ← Pop();Increment ESP by 4; (* Skip next 4 bytes of stack *)EBX ← Pop();EDX ← Pop();ECX ← Pop();EAX ← Pop();POPA/POPAD—Pop All General-Purpose RegistersVol.
2B 4-137INSTRUCTION SET REFERENCE, N-ZELSE (* OperandSize = 16, instruction = POPA *)DI ← Pop();SI ← Pop();BP ← Pop();Increment ESP by 2; (* Skip next 2 bytes of stack *)BX ← Pop();DX ← Pop();CX ← Pop();AX ← Pop();FI;FI;Flags AffectedNone.Protected Mode Exceptions#SS(0)If the starting or ending stack address is not within the stacksegment.#PF(fault-code)If a page fault occurs.#AC(0)If an unaligned memory reference is made while the currentprivilege level is 3 and alignment checking is enabled.#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#SSIf the starting or ending stack address is not within the stacksegment.#UDIf the LOCK prefix is used.Virtual-8086 Mode Exceptions#SS(0)If the starting or ending stack address is not within the stacksegment.#PF(fault-code)If a page fault occurs.#AC(0)If an unaligned memory reference is made while alignmentchecking is enabled.#UDIf the LOCK prefix is used.Compatibility Mode ExceptionsSame as for protected mode exceptions.64-Bit Mode Exceptions#UD4-138 Vol.
2BIf in 64-bit mode.POPA/POPAD—Pop All General-Purpose RegistersINSTRUCTION SET REFERENCE, N-ZPOPF/POPFD/POPFQ—Pop Stack into EFLAGS RegisterOpcodeInstruction64-BitModeCompat/Leg ModeDescription9DPOPFValidValidPop top of stack into lower 16 bits ofEFLAGS.9DPOPFDN.E.ValidPop top of stack into EFLAGS.REX.W + 9DPOPFQValidN.E.Pop top of stack and zero-extend intoRFLAGS.DescriptionPops a doubleword (POPFD) from the top of the stack (if the current operand-sizeattribute is 32) and stores the value in the EFLAGS register, or pops a word from thetop of the stack (if the operand-size attribute is 16) and stores it in the lower 16 bitsof the EFLAGS register (that is, the FLAGS register).
These instructions reverse theoperation of the PUSHF/PUSHFD instructions.The POPF (pop flags) and POPFD (pop flags double) mnemonics reference the sameopcode. The POPF instruction is intended for use when the operand-size attribute is16; the POPFD instruction is intended for use when the operand-size attribute is 32.Some assemblers may force the operand size to 16 for POPF and to 32 for POPFD.Others may treat the mnemonics as synonyms (POPF/POPFD) and use the setting ofthe operand-size attribute to determine the size of values to pop from the stack.The effect of POPF/POPFD on the EFLAGS register changes, depending on the modeof operation. When the processor is operating in protected mode at privilege level 0(or in real-address mode, the equivalent to privilege level 0), all non-reserved flagsin the EFLAGS register except RF1, VIP, VIF, and VM may be modified.
VIP, VIF andVM remain unaffected.When operating in protected mode with a privilege level greater than 0, but less thanor equal to IOPL, all flags can be modified except the IOPL field and VIP, VIF, and VM.Here, the IOPL flags are unaffected, the VIP and VIF flags are cleared, and the VMflag is unaffected. The interrupt flag (IF) is altered only when executing at a level atleast as privileged as the IOPL. If a POPF/POPFD instruction is executed with insufficient privilege, an exception does not occur but privileged bits do not change.When operating in virtual-8086 mode, the IOPL must be equal to 3 to usePOPF/POPFD instructions; VM, RF, IOPL, VIP, and VIF are unaffected. If the IOPL isless than 3, POPF/POPFD causes a general-protection exception (#GP).In 64-bit mode, use REX.W to pop the top of stack to RFLAGS. The mnemonicassigned is POPFQ (note that the 32-bit operand is not encodable).
POPFQ pops 641. RF is always zero after the execution of POPF. This is because POPF, like all instructions, clearsRF as it begins to execute.POPF/POPFD/POPFQ—Pop Stack into EFLAGS RegisterVol. 2B 4-139INSTRUCTION SET REFERENCE, N-Zbits from the stack, loads the lower 32 bits into RFLAGS, and zero extends the upperbits of RFLAGS.See Chapter 3 of the Intel® 64 and IA-32 Architectures Software Developer’sManual, Volume 1, for more information about the EFLAGS registers.OperationIF VM = 0 (* Not in Virtual-8086 Mode *)THEN IF CPL = 0THENIF OperandSize = 32;THENEFLAGS ← Pop(); (* 32-bit pop *)(* All non-reserved flags except RF, VIP, VIF, and VM can be modified;VIP and VIF are cleared; RF, VM, and all reserved bits are unaffected.
*)ELSE IF (Operandsize = 64)RFLAGS = Pop(); (* 64-bit pop *)(* All non-reserved flags except RF, VIP, VIF, and VM can be modified; VIPand VIF are cleared; RF, VM, and all reserved bits are unaffected.*)ELSE (* OperandSize = 16 *)EFLAGS[15:0] ← Pop(); (* 16-bit pop *)(* All non-reserved flags can be modified. *)FI;ELSE (* CPL > 0 *)IF OperandSize = 32THENIF CPL > IOPLTHENEFLAGS ← Pop(); (* 32-bit pop *)(* All non-reserved bits except IF, IOPL, RF, VIP, andVIF can be modified; IF, IOPL, RF, VM, and all reservedbits are unaffected; VIP and VIF are cleared.
*)ELSEEFLAGS ← Pop(); (* 32-bit pop *)(* All non-reserved bits except IOPL, RF, VIP, and VIF can bemodified; IOPL, RF, VM, and all reserved bits areunaffected; VIP and VIF are cleared. *)FI;ELSE IF (Operandsize = 64)IF CPL > IOPLTHENRFLAGS ← Pop(); (* 64-bit pop *)(* All non-reserved bits except IF, IOPL, RF, VIP, and4-140 Vol. 2BPOPF/POPFD/POPFQ—Pop Stack into EFLAGS RegisterINSTRUCTION SET REFERENCE, N-ZVIF can be modified; IF, IOPL, RF, VM, and all reservedbits are unaffected; VIP and VIF are cleared. *)ELSERFLAGS ← Pop(); (* 64-bit pop *)(* All non-reserved bits except IOPL, RF, VIP, and VIF can bemodified; IOPL, RF, VM, and all reserved bits areunaffected; VIP and VIF are cleared. *)FI;ELSE (* OperandSize = 16 *)EFLAGS[15:0] ← Pop(); (* 16-bit pop *)(* All non-reserved bits except IOPL can be modified; IOPL and allreserved bits are unaffected.
*)FI;FI;ELSE (* In Virtual-8086 Mode *)IF IOPL = 3THEN IF OperandSize = 32THENEFLAGS ← Pop();(* All non-reserved bits except VM, RF, IOPL, VIP, and VIF can bemodified; VM, RF, IOPL, VIP, VIF, and all reserved bits are unaffected. *)ELSEEFLAGS[15:0] ← Pop(); FI;(* All non-reserved bits except IOPL can be modified;IOPL and all reserved bits are unaffected. *)ELSE (* IOPL < 3 *)#GP(0); (* Trap to virtual-8086 monitor. *)FI;FI;FI;Flags AffectedAll flags may be affected; see the Operation section for details.Protected Mode Exceptions#SS(0)If the top of stack is not within the stack segment.#PF(fault-code)If a page fault occurs.#AC(0)If an unaligned memory reference is made while the currentprivilege level is 3 and alignment checking is enabled.#UDIf the LOCK prefix is used.POPF/POPFD/POPFQ—Pop Stack into EFLAGS RegisterVol.
2B 4-141INSTRUCTION SET REFERENCE, N-ZReal-Address Mode Exceptions#SSIf the top of stack is not within the stack segment.#UDIf the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)If the I/O privilege level is less than 3.If an attempt is made to execute the POPF/POPFD instructionwith an operand-size override prefix.#SS(0)If the top of stack is not within the stack segment.#PF(fault-code)If a page fault occurs.#AC(0)If an unaligned memory reference is made while alignmentchecking is enabled.#UDIf the LOCK prefix is used.Compatibility Mode ExceptionsSame as for protected mode exceptions.64-Bit Mode Exceptions#GP(0)If the memory address is in a non-canonical form.#SS(0)If the stack address is in a non-canonical form.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.4-142 Vol.
2BPOPF/POPFD/POPFQ—Pop Stack into EFLAGS RegisterINSTRUCTION SET REFERENCE, N-ZPOR—Bitwise Logical OROpcodeInstruction64-BitModeCompat/Leg ModeDescription0F EB /rPOR mm, mm/m64ValidValidBitwise OR of mm/m64 and mm.66 0F EB /rPOR xmm1,xmm2/m128ValidValidBitwise OR of xmm2/m128 andxmm1.DescriptionPerforms a bitwise logical OR operation on the source operand (second operand) andthe destination operand (first operand) and stores the result in the destinationoperand.
The source operand can be an MMX technology register or a 64-bit memorylocation or it can be an XMM register or a 128-bit memory location. The destinationoperand can be an MMX technology register or an XMM register. Each bit of the resultis set to 1 if either or both of the corresponding bits of the first and second operandsare 1; otherwise, it is set to 0.In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction toaccess additional registers (XMM8-XMM15).OperationDEST ← DEST OR SRC;Intel C/C++ Compiler Intrinsic EquivalentPOR__m64 _mm_or_si64(__m64 m1, __m64 m2)POR__m128i _mm_or_si128(__m128i m1, __m128i m2)Flags AffectedNone.Numeric ExceptionsNone.Protected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.(128-bit operations only) If a memory operand is not aligned ona 16-byte boundary, regardless of segment.#SS(0)POR—Bitwise Logical ORIf a memory operand effective address is outside the SSsegment limit.Vol.
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