Volume 2B Instruction Set Reference N-Z (794102), страница 13
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2BPHSUBW/PHSUBD — Packed Horizontal SubtractINSTRUCTION SET REFERENCE, N-ZPHSUBSW — Packed Horizontal Subtract and SaturateOpcodeInstruction64-BitModeCompat/Leg ModeDescription0F 38 07 /rPHSUBSW mm1,mm2/m64ValidValidSubtract 16-bit signedinteger horizontally, packsaturated integers to MM1.66 0F 38 07 /rPHSUBSWxmm1,xmm2/m128ValidValidSubtract 16-bit signedinteger horizontally, packsaturated integers toXMM1DescriptionPHSUBSW performs horizontal subtraction on each adjacent pair of 16-bit signedintegers by subtracting the most significant word from the least significant word ofeach pair in the source and destination operands.
The signed, saturated 16-bitresults are packed to the destination operand (first operand). Both operands can beMMX or XMM register. When the source operand is a 128-bit memory operand, theoperand must be aligned on a 16-byte boundary or a general-protection exception(#GP) will be generated.In 64-bit mode, use the REX prefix to access additional registers.OperationPHSUBSW with 64-bit operands:mm1[15-0] = SaturateToSignedWord(mm1[15-0] - mm1[31-16]);mm1[31-16] = SaturateToSignedWord(mm1[47-32] - mm1[63-48]);mm1[47-32] = SaturateToSignedWord(mm2/m64[15-0] - mm2/m64[31-16]);mm1[63-48] = SaturateToSignedWord(mm2/m64[47-32] - mm2/m64[63-48]);PHSUBSW with 128-bit operands:xmm1[15-0] = SaturateToSignedWord(xmm1[15-0] - xmm1[31-16]);xmm1[31-16] = SaturateToSignedWord(xmm1[47-32] - xmm1[63-48]);xmm1[47-32] = SaturateToSignedWord(xmm1[79-64] - xmm1[95-80]);xmm1[63-48] = SaturateToSignedWord(xmm1[111-96] - xmm1[127-112]);xmm1[79-64] = SaturateToSignedWord(xmm2/m128[15-0] - xmm2/m128[31-16]);xmm1[95-80] =SaturateToSignedWord(xmm2/m128[47-32] - xmm2/m128[63-48]);xmm1[111-96] =SaturateToSignedWord(xmm2/m128[79-64] - xmm2/m128[95-80]);xmm1[127-112]= SaturateToSignedWord(xmm2/m128[111-96] - xmm2/m128[127-112]);PHSUBSW — Packed Horizontal Subtract and SaturateVol.
2B 4-85INSTRUCTION SET REFERENCE, N-ZIntel C/C++ Compiler Intrinsic EquivalentPHSUBSW __m64 _mm_hsubs_pi16 (__m64 a, __m64 b)PHSUBSW __m128i _mm_hsubs_epi16 (__m128i a, __m128i b)Protected Mode Exceptions#GP(0)if a memory operand effective address is outside the CS, DS, ES,FS or GS segments.If not aligned on 16-byte boundary, regardless of segment(128-bit operations only).#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#UDIf CR0.EM = 1.If CR4.OSFXSR(bit 9) = 0 (128-bit operations only).If CPUID.SSSE3(ECX bit 9) = 0.If the LOCK prefix is used.#NMIf TS bit in CR0 is set.#MFIf there is a pending x87 FPU exception (64-bit operations only).#AC(0)If alignment checking is enabled and unaligned memory reference is made while the current privilege level is 3 (64-bit operations only).Real Mode Exceptions#GP(0)If any part of the operand lies outside of the effective addressspace from 0 to 0FFFFH.If not aligned on 16-byte boundary, regardless of segment(128-bit operations only).#UDIf CR0.EM = 1.If CR4.OSFXSR(bit 9) = 0 (128-bit operations only).If CPUID.SSSE3(ECX bit 9) = 0.If the LOCK prefix is used.#NMIf TS bit in CR0 is set.#MFIf there is a pending x87 FPU exception (64-bit operations only).Virtual 8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and unaligned memory reference is made (64-bit operations only).4-86 Vol.
2BPHSUBSW — Packed Horizontal Subtract and SaturateINSTRUCTION SET REFERENCE, N-ZCompatibility Mode ExceptionsSame as for protected mode exceptions.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.(128-bit operations only) If memory operand is not aligned on a16-byte boundary, regardless of segment.#UDIf CR0.EM[bit 2] = 1.(128-bit operations only) If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:ECX.SSSE3[bit 9] = 0.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made while the current privilegelevel is 3.PHSUBSW — Packed Horizontal Subtract and SaturateVol.
2B 4-87INSTRUCTION SET REFERENCE, N-ZPINSRW—Insert WordOpcodeInstruction64-BitModeCompat/Leg ModeDescription0F C4 /r ibPINSRW mm,r32/m16, imm8ValidValidInsert the low word fromr32 or from m16 into mmat the word positionspecified by imm8REX.W + 0F C4 /r ibPINSRW mm,r64/m16, imm8ValidN.E.Insert the low word fromr64 or from m16 into mmat the word positionspecified by imm866 0F C4 /r ibPINSRW xmm,r32/m16, imm8ValidValidMove the low word of r32or from m16 into xmm atthe word position specifiedby imm8.66 REX.W 0F C4 /r ibPINSRW xmm,r64/m16, imm8ValidN.E.Move the low word of r64or from m16 into xmm atthe word position specifiedby imm8.DescriptionCopies a word from the source operand (second operand) and inserts it in the destination operand (first operand) at the location specified with the count operand (thirdoperand).
(The other words in the destination register are left untouched.) Thesource operand can be a general-purpose register or a 16-bit memory location.(When the source operand is a general-purpose register, the low word of the registeris copied.) The destination operand can be an MMX technology register or an XMMregister. The count operand is an 8-bit immediate. When specifying a word location inan MMX technology register, the 2 least-significant bits of the count operand specifythe location; for an XMM register, the 3 least-significant bits specify the location.In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction toaccess additional registers (XMM8-XMM15, R8-15).
Use of REX.W permits the use of64 bit general purpose registers.OperationPINSRW instruction with 64-bit source operand:SEL ← COUNT AND 3H;CASE (Determine word position) OFSEL ← 0:MASK ← 000000000000FFFFH;SEL ← 1:MASK ← 00000000FFFF0000H;SEL ← 2:MASK ← 0000FFFF00000000H;4-88 Vol. 2BPINSRW—Insert WordINSTRUCTION SET REFERENCE, N-ZSEL ← 3:MASK ← FFFF000000000000H;DEST ← (DEST AND NOT MASK) OR (((SRC << (SEL ∗ 16)) AND MASK);PINSRW instruction with 128-bit source operand:SEL ← COUNT AND 7H;CASE (Determine word position) OFSEL ← 0:MASK ← 0000000000000000000000000000FFFFH;SEL ← 1:MASK ← 000000000000000000000000FFFF0000H;SEL ← 2:MASK ← 00000000000000000000FFFF00000000H;SEL ← 3:MASK ← 0000000000000000FFFF000000000000H;SEL ← 4:MASK ← 000000000000FFFF0000000000000000H;SEL ← 5:MASK ← 00000000FFFF00000000000000000000H;SEL ← 6:MASK ← 0000FFFF000000000000000000000000H;SEL ← 7:MASK ← FFFF0000000000000000000000000000H;DEST ← (DEST AND NOT MASK) OR (((SRC << (SEL ∗ 16)) AND MASK);Intel C/C++ Compiler Intrinsic EquivalentPINSRW__m64 _mm_insert_pi16 (__m64 a, int d, int n)PINSRW__m128i _mm_insert_epi16 ( __m128i a, int b, int imm)Flags AffectedNone.Numeric ExceptionsNone.Protected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.#UDIf CR0.EM[bit 2] = 1.(128-bit operations only) If CR4.OSFXSR[bit 9] = 0.(128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made while the current privilegelevel is 3.PINSRW—Insert WordVol.
2B 4-89INSTRUCTION SET REFERENCE, N-ZReal-Address Mode Exceptions#GP(0)If any part of the operand lies outside of the effective addressspace from 0 to FFFFH.#UDIf CR0.EM[bit 2] = 1.(128-bit operations only) If CR4.OSFXSR[bit 9] = 0.(128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#UDIf CR0.EM[bit 2] = 1.(128-bit operations only) If CR4.OSFXSR[bit 9] = 0.(128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.4-90 Vol.
2BPINSRW—Insert WordINSTRUCTION SET REFERENCE, N-ZPMADDUBSW — Multiply and Add Packed Signed and Unsigned Bytes64-BitModeCompat/Leg ModePMADDUBSWmm1, mm2/m64ValidValidMultiply signed andunsigned bytes, addhorizontal pair of signedwords, pack saturatedsigned-words to MM1.PMADDUBSWxmm1,xmm2/m128ValidValidMultiply signed andunsigned bytes, addhorizontal pair of signedwords, pack saturatedsigned-words to XMM1.OpcodeInstruction0F 38 04 /r66 0F 38 04 /rDescriptionDescriptionPMADDUBSW multiplies vertically each unsigned byte of the destination operand(first operand) with the corresponding signed byte of the source operand (secondoperand), producing intermediate signed 16-bit integers. Each adjacent pair ofsigned words is added and the saturated result is packed to the destination operand.For example, the lowest-order bytes (bits 7-0) in the source and destination operands are multiplied and the intermediate signed word result is added with the corresponding intermediate result from the 2nd lowest-order bytes (bits 15-8) of theoperands; the sign-saturated result is stored in the lowest word of the destinationregister (15-0).
The same operation is performed on the other pairs of adjacentbytes. Both operands can be MMX register or XMM registers. When the sourceoperand is a 128-bit memory operand, the operand must be aligned on a 16-byteboundary or a general-protection exception (#GP) will be generated.In 64-bit mode, use the REX prefix to access additional registers.OperationPMADDUBSW with 64 bit operands:DEST[15-0] = SaturateToSignedWord(SRC[15-8]*DEST[15-8]+SRC[7-0]*DEST[7-0]);DEST[31-16] = SaturateToSignedWord(SRC[31-24]*DEST[31-24]+SRC[23-16]*DEST[23-16]);DEST[47-32] = SaturateToSignedWord(SRC[47-40]*DEST[47-40]+SRC[39-32]*DEST[39-32]);DEST[63-48] = SaturateToSignedWord(SRC[63-56]*DEST[63-56]+SRC[55-48]*DEST[55-48]);PMADDUBSW with 128 bit operands:DEST[15-0] = SaturateToSignedWord(SRC[15-8]* DEST[15-8]+SRC[7-0]*DEST[7-0]);// Repeat operation for 2nd through 7th wordPMADDUBSW — Multiply and Add Packed Signed and Unsigned BytesVol.
2B 4-91INSTRUCTION SET REFERENCE, N-ZSRC1/DEST[127-112] = SaturateToSignedWord(SRC[127-120]*DEST[127-120]+ SRC[119112]* DEST[119-112]);Intel C/C++ Compiler Intrinsic EquivalentsPMADDUBSW__m64 _mm_maddubs_pi16 (__m64 a, __m64 b)PMADDUBSW__m128i _mm_maddubs_epi16 (__m128i a, __m128i b)Protected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS or GS segments.(128-bit operations only) If not aligned on 16-byte boundary,regardless of segment.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#UDIf CR0.EM = 1.If CR4.OSFXSR(bit 9) = 0 (128-bit operations only)If CPUID.SSSE3(ECX bit 9) = 0.If the LOCK prefix is used.#NMIf TS bit in CR0 is set.#MF(64-bit operations only) If there is a pending x87 FPU exception.#AC(0)(64-bit operations only) If alignment checking is enabled andunaligned memory reference is made while the current privilegelevel is 3.Real Mode Exceptions#GP(0)If any part of the operand lies outside of the effective addressspace from 0 to 0FFFFH.(128-bit operations only) If not aligned on 16-byte boundary,regardless of segment.#UDIf CR0.EM = 1.(128-bit operations only) If CR4.OSFXSR(bit 9) = 0.If CPUID.SSSE3(ECX bit 9) = 0.If the LOCK prefix is used.#NMIf TS bit in CR0 is set.#MF(64-bit operations only) If there is a pending x87 FPU exception.Virtual 8086 Mode ExceptionsSame exceptions as in real address mode.4-92 Vol.
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