Volume 2B Instruction Set Reference N-Z (794102), страница 6
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2B 4-37INSTRUCTION SET REFERENCE, N-ZFlags AffectedNone.Protected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.(128-bit operations only) If a memory operand is not aligned ona 16-byte boundary, regardless of segment.#SS(0)#UDIf a memory operand effective address is outside the SSsegment limit.If CR0.EM[bit 2] = 1.128-bit operations will generate #UD only if CR4.OSFXSR[bit 9]= 0.
Execution of 128-bit instructions on a non-SSE2 capableprocessor (one that is MMX technology capable) will result in theinstruction operating on the mm registers, not #UD.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made while the current privilegelevel is 3.Real-Address Mode Exceptions#GP(0)(128-bit operations only) If a memory operand is not aligned ona 16-byte boundary, regardless of segment.If any part of the operand lies outside of the effective addressspace from 0 to FFFFH.#UDIf CR0.EM[bit 2] = 1.128-bit operations will generate #UD only if CR4.OSFXSR[bit 9]= 0.
Execution of 128-bit instructions on a non-SSE2 capableprocessor (one that is MMX technology capable) will result in theinstruction operating on the mm registers, not #UD.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)4-38 Vol. 2BFor a page fault.PADDB/PADDW/PADDD—Add Packed IntegersINSTRUCTION SET REFERENCE, N-Z#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made.Compatibility Mode ExceptionsSame as for protected mode exceptions.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.(128-bit operations only) If memory operand is not aligned on a16-byte boundary, regardless of segment.#UDIf CR0.EM[bit 2] = 1.(128-bit operations only) If CR4.OSFXSR[bit 9] = 0.(128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made while the current privilegelevel is 3.PADDB/PADDW/PADDD—Add Packed IntegersVol.
2B 4-39INSTRUCTION SET REFERENCE, N-ZPADDQ—Add Packed Quadword IntegersOpcodeInstruction64-BitModeCompat/Leg ModeDescription0F D4 /rPADDQ mm1,mm2/m64ValidValidAdd quadword integermm2/m64 to mm1.66 0F D4 /rPADDQ xmm1,xmm2/m128ValidValidAdd packed quadword integersxmm2/m128 to xmm1.DescriptionAdds the first operand (destination operand) to the second operand (source operand)and stores the result in the destination operand.
The source operand can be a quadword integer stored in an MMX technology register or a 64-bit memory location, or itcan be two packed quadword integers stored in an XMM register or an 128-bitmemory location. The destination operand can be a quadword integer stored in anMMX technology register or two packed quadword integers stored in an XMM register.When packed quadword operands are used, a SIMD add is performed. When a quadword result is too large to be represented in 64 bits (overflow), the result is wrappedaround and the low 64 bits are written to the destination element (that is, the carryis ignored).Note that the PADDQ instruction can operate on either unsigned or signed (two’scomplement notation) integers; however, it does not set bits in the EFLAGS registerto indicate overflow and/or a carry.
To prevent undetected overflow conditions, software must control the ranges of the values operated on.In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction toaccess additional registers (XMM8-XMM15).OperationPADDQ instruction with 64-Bit operands:DEST[63:0] ← DEST[63:0] + SRC[63:0];PADDQ instruction with 128-Bit operands:DEST[63:0] ← DEST[63:0] + SRC[63:0];DEST[127:64] ← DEST[127:64] + SRC[127:64];Intel C/C++ Compiler Intrinsic EquivalentsPADDQ__m64 _mm_add_si64 (__m64 a, __m64 b)PADDQ__m128i _mm_add_epi64 ( __m128i a, __m128i b)Flags AffectedNone.4-40 Vol.
2BPADDQ—Add Packed Quadword IntegersINSTRUCTION SET REFERENCE, N-ZNumeric ExceptionsNone.Protected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.(128-bit operations only) If a memory operand is not aligned ona 16-byte boundary, regardless of segment.#SS(0)#UDIf a memory operand effective address is outside the SSsegment limit.If CR0.EM[bit 2] = 1.(128-bit operations only) If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made while the current privilegelevel is 3.Real-Address Mode Exceptions#GP(0)(128-bit operations only) If a memory operand is not aligned ona 16-byte boundary, regardless of segment.If any part of the operand lies outside of the effective addressspace from 0 to FFFFH.#UDIf CR0.EM[bit 2] = 1.(128-bit operations only) If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made.PADDQ—Add Packed Quadword IntegersVol.
2B 4-41INSTRUCTION SET REFERENCE, N-ZCompatibility Mode ExceptionsSame as for protected mode exceptions.64-Bit Mode Exceptions#SS(0)#GP(0)If a memory address referencing the SS segment is in a noncanonical form.If the memory address is in a non-canonical form.(128-bit operations only) If memory operand is not aligned on a16-byte boundary, regardless of segment.#UDIf CR0.EM[bit 2] = 1.(128-bit operations only) If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made while the current privilegelevel is 3.4-42 Vol. 2BPADDQ—Add Packed Quadword IntegersINSTRUCTION SET REFERENCE, N-ZPADDSB/PADDSW—Add Packed Signed Integers with SignedSaturationOpcodeInstruction64-BitModeCompat/Leg ModeDescription0F EC /rPADDSB mm,mm/m64ValidValidAdd packed signed byte integersfrom mm/m64 and mm andsaturate the results.66 0F EC /rPADDSB xmm1,xmm2/m128ValidValidAdd packed signed byte integersfrom xmm2/m128 and xmm1saturate the results.0F ED /rPADDSW mm,mm/m64ValidValidAdd packed signed word integersfrom mm/m64 and mm andsaturate the results.66 0F ED /rPADDSW xmm1,xmm2/m128ValidValidAdd packed signed word integersfrom xmm2/m128 and xmm1and saturate the results.DescriptionPerforms a SIMD add of the packed signed integers from the source operand (secondoperand) and the destination operand (first operand), and stores the packed integerresults in the destination operand.
See Figure 9-4 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for an illustration of a SIMD operation. Overflow is handled with signed saturation, as described in the followingparagraphs.These instructions can operate on either 64-bit or 128-bit operands. When operatingon 64-bit operands, the destination operand must be an MMX technology registerand the source operand can be either an MMX technology register or a 64-bitmemory location. When operating on 128-bit operands, the destination operandmust be an XMM register and the source operand can be either an XMM register or a128-bit memory location.The PADDSB instruction adds packed signed byte integers.
When an individual byteresult is beyond the range of a signed byte integer (that is, greater than 7FH or lessthan 80H), the saturated value of 7FH or 80H, respectively, is written to the destination operand.The PADDSW instruction adds packed signed word integers. When an individual wordresult is beyond the range of a signed word integer (that is, greater than 7FFFH orless than 8000H), the saturated value of 7FFFH or 8000H, respectively, is written tothe destination operand.In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction toaccess additional registers (XMM8-XMM15).PADDSB/PADDSW—Add Packed Signed Integers with Signed SaturationVol. 2B 4-43INSTRUCTION SET REFERENCE, N-ZOperationPADDSB instruction with 64-bit operands:DEST[7:0] ← SaturateToSignedByte(DEST[7:0] + SRC (7:0]);(* Repeat add operation for 2nd through 7th bytes *)DEST[63:56] ← SaturateToSignedByte(DEST[63:56] + SRC[63:56] );PADDSB instruction with 128-bit operands:DEST[7:0] ←SaturateToSignedByte (DEST[7:0] + SRC[7:0]);(* Repeat add operation for 2nd through 14th bytes *)DEST[127:120] ← SaturateToSignedByte (DEST[111:120] + SRC[127:120]);PADDSW instruction with 64-bit operandsDEST[15:0] ← SaturateToSignedWord(DEST[15:0] + SRC[15:0] );(* Repeat add operation for 2nd and 7th words *)DEST[63:48] ← SaturateToSignedWord(DEST[63:48] + SRC[63:48] );PADDSW instruction with 128-bit operandsDEST[15:0] ← SaturateToSignedWord (DEST[15:0] + SRC[15:0]);(* Repeat add operation for 2nd through 7th words *)DEST[127:112] ← SaturateToSignedWord (DEST[127:112] + SRC[127:112]);Intel C/C++ Compiler Intrinsic EquivalentsPADDSB__m64 _mm_adds_pi8(__m64 m1, __m64 m2)PADDSB__m128i _mm_adds_epi8 ( __m128i a, __m128i b)PADDSW__m64 _mm_adds_pi16(__m64 m1, __m64 m2)PADDSW__m128i _mm_adds_epi16 ( __m128i a, __m128i b)Flags AffectedNone.Protected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.(128-bit operations only) If a memory operand is not aligned ona 16-byte boundary, regardless of segment.#SS(0)#UDIf a memory operand effective address is outside the SSsegment limit.If CR0.EM[bit 2] = 1.128-bit operations will generate #UD only if CR4.OSFXSR[bit 9]= 0.
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