Volume 2B Instruction Set Reference N-Z (794102), страница 3
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2BORPS—Bitwise Logical OR of Single-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, N-ZReal-Address Mode Exceptions#GP(0)If a memory operand is not aligned on a 16-byte boundary,regardless of segment.If any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.Compatibility Mode ExceptionsSame as for protected mode exceptions.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.If memory operand is not aligned on a 16-byte boundary,regardless of segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.ORPS—Bitwise Logical OR of Single-Precision Floating-Point ValuesVol.
2B 4-15INSTRUCTION SET REFERENCE, N-ZOUT—Output to PortOpcode*Instruction64-BitModeCompat/Leg ModeDescriptionE6 ibOUT imm8, ALValidValidOutput byte in AL to I/O portaddress imm8.E7 ibOUT imm8, AXValidValidOutput word in AX to I/O portaddress imm8.E7 ibOUT imm8, EAXValidValidOutput doubleword in EAX to I/Oport address imm8.EEOUT DX, ALValidValidOutput byte in AL to I/O portaddress in DX.EFOUT DX, AXValidValidOutput word in AX to I/O portaddress in DX.EFOUT DX, EAXValidValidOutput doubleword in EAX to I/Oport address in DX.NOTES:* See IA-32 Architecture Compatibility section below.DescriptionCopies the value from the second operand (source operand) to the I/O port specifiedwith the destination operand (first operand).
The source operand can be register AL,AX, or EAX, depending on the size of the port being accessed (8, 16, or 32 bits,respectively); the destination operand can be a byte-immediate or the DX register.Using a byte immediate allows I/O port addresses 0 to 255 to be accessed; using theDX register as a source operand allows I/O ports from 0 to 65,535 to be accessed.The size of the I/O port being accessed is determined by the opcode for an 8-bit I/Oport or by the operand-size attribute of the instruction for a 16- or 32-bit I/O port.At the machine code level, I/O instructions are shorter when accessing 8-bit I/Oports. Here, the upper eight bits of the port address will be 0.This instruction is only useful for accessing I/O ports located in the processor’s I/Oaddress space.
See Chapter 13, “Input/Output,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for more information on accessing I/Oports in the I/O address space.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.IA-32 Architecture CompatibilityAfter executing an OUT instruction, the Pentium® processor insures that the EWBE#pin has been sampled active before it begins to execute the next instruction.
(Notethat the instruction can be prefetched if EWBE# is not active, but it will not be4-16 Vol. 2BOUT—Output to PortINSTRUCTION SET REFERENCE, N-Zexecuted until the EWBE# pin is sampled active.) Only the Pentium processor familyhas the EWBE# pin.OperationIF ((PE = 1) and ((CPL > IOPL) or (VM = 1)))THEN (* Protected mode with CPL > IOPL or virtual-8086 mode *)IF (Any I/O Permission Bit for I/O port being accessed = 1)THEN (* I/O operation is not allowed *)#GP(0);ELSE ( * I/O operation is allowed *)DEST ← SRC; (* Writes to selected I/O port *)FI;ELSE (Real Mode or Protected Mode with CPL ≤ IOPL *)DEST ← SRC; (* Writes to selected I/O port *)FI;Flags AffectedNone.Protected Mode Exceptions#GP(0)If the CPL is greater than (has less privilege) the I/O privilegelevel (IOPL) and any of the corresponding I/O permission bits inTSS for the I/O port being accessed is 1.#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#UDIf the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)If any of the I/O permission bits in the TSS for the I/O port beingaccessed is 1.#PF(fault-code)If a page fault occurs.#UDIf the LOCK prefix is used.Compatibility Mode ExceptionsSame as protected mode exceptions.64-Bit Mode ExceptionsSame as protected mode exceptions.OUT—Output to PortVol.
2B 4-17INSTRUCTION SET REFERENCE, N-ZOUTS/OUTSB/OUTSW/OUTSD—Output String to PortOpcode*Instruction64-Bit Mode Compat/Leg ModeDescription6EOUTS DX, m8ValidValidOutput byte from memorylocation specified in DS:(E)SI orRSI to I/O port specified in DX**.6FOUTS DX, m16ValidValidOutput word from memorylocation specified in DS:(E)SI orRSI to I/O port specified in DX**.6FOUTS DX, m32ValidValidOutput doubleword frommemory location specified inDS:(E)SI or RSI to I/O portspecified in DX**.6EOUTSBValidValidOutput byte from memorylocation specified in DS:(E)SI orRSI to I/O port specified in DX**.6FOUTSWValidValidOutput word from memorylocation specified in DS:(E)SI orRSI to I/O port specified in DX**.6FOUTSDValidValidOutput doubleword frommemory location specified inDS:(E)SI or RSI to I/O portspecified in DX**.NOTES:* See IA-32 Architecture Compatibility section below.** In 64-bit mode, only 64-bit (RSI) and 32-bit (ESI) address sizes are supported.
In non-64-bitmode, only 32-bit (ESI) and 16-bit (SI) address sizes are supported.DescriptionCopies data from the source operand (second operand) to the I/O port specified withthe destination operand (first operand). The source operand is a memory location,the address of which is read from either the DS:SI, DS:ESI or the RSI registers(depending on the address-size attribute of the instruction, 16, 32 or 64, respectively). (The DS segment may be overridden with a segment override prefix.) Thedestination operand is an I/O port address (from 0 to 65,535) that is read from theDX register. The size of the I/O port being accessed (that is, the size of the sourceand destination operands) is determined by the opcode for an 8-bit I/O port or by theoperand-size attribute of the instruction for a 16- or 32-bit I/O port.At the assembly-code level, two forms of this instruction are allowed: the “explicitoperands” form and the “no-operands” form.
The explicit-operands form (specifiedwith the OUTS mnemonic) allows the source and destination operands to be specifiedexplicitly. Here, the source operand should be a symbol that indicates the size of the4-18 Vol. 2BOUTS/OUTSB/OUTSW/OUTSD—Output String to PortINSTRUCTION SET REFERENCE, N-ZI/O port and the source address, and the destination operand must be DX.
Thisexplicit-operands form is provided to allow documentation; however, note that thedocumentation provided by this form can be misleading. That is, the source operandsymbol must specify the correct type (size) of the operand (byte, word, or doubleword), but it does not have to specify the correct location. The location is alwaysspecified by the DS:(E)SI or RSI registers, which must be loaded correctly before theOUTS instruction is executed.The no-operands form provides “short forms” of the byte, word, and doublewordversions of the OUTS instructions. Here also DS:(E)SI is assumed to be the sourceoperand and DX is assumed to be the destination operand.
The size of the I/O port isspecified with the choice of mnemonic: OUTSB (byte), OUTSW (word), or OUTSD(doubleword).After the byte, word, or doubleword is transferred from the memory location to theI/O port, the SI/ESI/RSI register is incremented or decremented automaticallyaccording to the setting of the DF flag in the EFLAGS register. (If the DF flag is 0, the(E)SI register is incremented; if the DF flag is 1, the SI/ESI/RSI register is decremented.) The SI/ESI/RSI register is incremented or decremented by 1 for byte operations, by 2 for word operations, and by 4 for doubleword operations.The OUTS, OUTSB, OUTSW, and OUTSD instructions can be preceded by the REPprefix for block input of ECX bytes, words, or doublewords. See “REP/REPE/REPZ/REPNE/REPNZ—Repeat String Operation Prefix” in this chapter for a description ofthe REP prefix.
This instruction is only useful for accessing I/O ports located in theprocessor’s I/O address space. See Chapter 13, “Input/Output,” in the Intel® 64 andIA-32 Architectures Software Developer’s Manual, Volume 1, for more information onaccessing I/O ports in the I/O address space.In 64-bit mode, the default operand size is 32 bits; operand size is not promoted bythe use of REX.W. In 64-bit mode, the default address size is 64 bits, and 64-bitaddress is specified using RSI by default. 32-bit address using ESI is support usingthe prefix 67H, but 16-bit address is not supported in 64-bit mode.IA-32 Architecture CompatibilityAfter executing an OUTS, OUTSB, OUTSW, or OUTSD instruction, the Pentiumprocessor insures that the EWBE# pin has been sampled active before it begins toexecute the next instruction. (Note that the instruction can be prefetched if EWBE#is not active, but it will not be executed until the EWBE# pin is sampled active.) Onlythe Pentium processor family has the EWBE# pin.For the Pentium 4, Intel® Xeon®, and P6 processor family, upon execution of anOUTS, OUTSB, OUTSW, or OUTSD instruction, the processor will not execute the nextinstruction until the data phase of the transaction is complete.OperationIF ((PE = 1) and ((CPL > IOPL) or (VM = 1)))THEN (* Protected mode with CPL > IOPL or virtual-8086 mode *)OUTS/OUTSB/OUTSW/OUTSD—Output String to PortVol.
2B 4-19INSTRUCTION SET REFERENCE, N-ZIF (Any I/O Permission Bit for I/O port being accessed = 1)THEN (* I/O operation is not allowed *)#GP(0);ELSE (* I/O operation is allowed *)DEST ← SRC; (* Writes to I/O port *)FI;ELSE (Real Mode or Protected Mode or 64-Bit Mode with CPL ≤ IOPL *)DEST ← SRC; (* Writes to I/O port *)FI;Byte transfer:IF 64-bit modeThenIF 64-Bit Address SizeTHENIF DF = 0THEN RSI ← RSI RSI + 1;ELSE RSI ← RSI or – 1;FI;ELSE (* 32-Bit Address Size *)IF DF = 0THENESI ← ESI + 1;ELSEESI ← ESI – 1;FI;FI;ELSEIF DF = 0THEN(E)SI ← (E)SI + 1;ELSE (E)SI ← (E)SI – 1;FI;FI;Word transfer:IF 64-bit modeThenIF 64-Bit Address SizeTHENIF DF = 0THEN RSI ← RSI RSI + 2;ELSE RSI ← RSI or – 2;FI;ELSE (* 32-Bit Address Size *)IF DF = 0THENESI ← ESI + 2;4-20 Vol. 2BOUTS/OUTSB/OUTSW/OUTSD—Output String to PortINSTRUCTION SET REFERENCE, N-ZELSEESI ← ESI – 2;FI;FI;ELSEIF DF = 0THEN(E)SI ← (E)SI + 2;ELSE (E)SI ← (E)SI – 2;FI;FI;Doubleword transfer:IF 64-bit modeThenIF 64-Bit Address SizeTHENIF DF = 0THEN RSI ← RSI RSI + 4;ELSE RSI ← RSI or – 4;FI;ELSE (* 32-Bit Address Size *)IF DF = 0THENESI ← ESI + 4;ELSEESI ← ESI – 4;FI;FI;ELSEIF DF = 0THEN(E)SI ← (E)SI + 4;ELSE (E)SI ← (E)SI – 4;FI;FI;Flags AffectedNone.Protected Mode Exceptions#GP(0)If the CPL is greater than (has less privilege) the I/O privilegelevel (IOPL) and any of the corresponding I/O permission bits inTSS for the I/O port being accessed is 1.If a memory operand effective address is outside the limit of theCS, DS, ES, FS, or GS segment.If the segment register contains a NULL segment selector.#PF(fault-code)If a page fault occurs.OUTS/OUTSB/OUTSW/OUTSD—Output String to PortVol.
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