Volume 2B Instruction Set Reference N-Z (794102), страница 2
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Using a REXprefix in the form of REX.W promotes operation to 64 bits. See the summary chart atthe beginning of this section for encoding data and limits.OperationDEST ← NOT DEST;Flags AffectedNone.Protected Mode Exceptions#GP(0)If the destination operand points to a non-writable segment.If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register contains a NULL segmentselector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.NOT—One's Complement NegationVol.
2B 4-7INSTRUCTION SET REFERENCE, N-Z#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used but the destination is not a memoryoperand.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.#UDIf the LOCK prefix is used but the destination is not a memoryoperand.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.#UDIf the LOCK prefix is used but the destination is not a memoryoperand.Compatibility Mode ExceptionsSame as for protected mode exceptions.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used but the destination is not a memoryoperand.4-8 Vol.
2BNOT—One's Complement NegationINSTRUCTION SET REFERENCE, N-ZOR—Logical Inclusive OROpcodeInstruction64-BitModeCompat/Leg ModeDescription0C ibOR AL, imm8ValidValidAL OR imm8.0D iwOR AX, imm16ValidValidAX OR imm16.0D idOR EAX, imm32ValidValidEAX OR imm32.REX.W + 0D idOR RAX, imm32ValidN.E.RAX OR imm32 (signextended).80 /1 ibOR r/m8, imm8ValidValidr/m8 OR imm8.REX + 80 /1 ibOR r/m8*, imm8ValidN.E.r/m8 OR imm8.81 /1 iwOR r/m16, imm16ValidValidr/m16 OR imm16.81 /1 idOR r/m32, imm32ValidValidr/m32 OR imm32.REX.W + 81 /1 idOR r/m64, imm32ValidN.E.r/m64 OR imm32 (signextended).83 /1 ibOR r/m16, imm8ValidValidr/m16 OR imm8 (signextended).83 /1 ibOR r/m32, imm8ValidValidr/m32 OR imm8 (signextended).REX.W + 83 /1 ibOR r/m64, imm8ValidN.E.r/m64 OR imm8 (signextended).08 /rOR r/m8, r8ValidValidr/m8 OR r8.REX + 08 /rOR r/m8*, r8*ValidN.E.r/m8 OR r8.09 /rOR r/m16, r16ValidValidr/m16 OR r16.09 /rOR r/m32, r32ValidValidr/m32 OR r32.REX.W + 09 /rOR r/m64, r64ValidN.E.r/m64 OR r64.0A /rOR r8, r/m8ValidValidr8 OR r/m8.REX + 0A /rOR r8*, r/m8*ValidN.E.r8 OR r/m8.0B /rOR r16, r/m16ValidValidr16 OR r/m16.0B /rOR r32, r/m32ValidValidr32 OR r/m32.REX.W + 0B /rOR r64, r/m64ValidN.E.r64 OR r/m64.NOTES:* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix isused: AH, BH, CH, DH.OR—Logical Inclusive ORVol.
2B 4-9INSTRUCTION SET REFERENCE, N-ZDescriptionPerforms a bitwise inclusive OR operation between the destination (first) and source(second) operands and stores the result in the destination operand location. Thesource operand can be an immediate, a register, or a memory location; the destination operand can be a register or a memory location. (However, two memory operands cannot be used in one instruction.) Each bit of the result of the OR instruction isset to 0 if both corresponding bits of the first and second operands are 0; otherwise,each bit is set to 1.This instruction can be used with a LOCK prefix to allow the instruction to beexecuted atomically.In 64-bit mode, the instruction’s default operation size is 32 bits.
Using a REX prefixin the form of REX.R permits access to additional registers (R8-R15). Using a REXprefix in the form of REX.W promotes operation to 64 bits. See the summary chart atthe beginning of this section for encoding data and limits.OperationDEST ← DEST OR SRC;Flags AffectedThe OF and CF flags are cleared; the SF, ZF, and PF flags are set according to theresult.
The state of the AF flag is undefined.Protected Mode Exceptions#GP(0)If the destination operand points to a non-writable segment.If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register contains a NULL segmentselector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used but the destination is not a memoryoperand.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.4-10 Vol.
2BOR—Logical Inclusive ORINSTRUCTION SET REFERENCE, N-Z#UDIf the LOCK prefix is used but the destination is not a memoryoperand.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.#UDIf the LOCK prefix is used but the destination is not a memoryoperand.Compatibility Mode ExceptionsSame as for protected mode exceptions.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used but the destination is not a memoryoperand.OR—Logical Inclusive ORVol.
2B 4-11INSTRUCTION SET REFERENCE, N-ZORPD—Bitwise Logical OR of Double-Precision Floating-Point ValuesOpcodeInstruction64-BitModeCompat/Leg ModeDescription66 0F 56 /rORPD xmm1, xmm2/m128ValidValidBitwise OR of xmm2/m128and xmm1.DescriptionPerforms a bitwise logical OR of the two packed double-precision floating-pointvalues from the source operand (second operand) and the destination operand (firstoperand), and stores the result in the destination operand. The source operand canbe an XMM register or a 128-bit memory location.
The destination operand is an XMMregister.In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction toaccess additional registers (XMM8-XMM15).OperationDEST[127:0] ← DEST[127:0] BitwiseOR SRC[127:0];Intel® C/C++ Compiler Intrinsic EquivalentORPD__m128d _mm_or_pd(__m128d a, __m128d b)SIMD Floating-Point ExceptionsNone.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.4-12 Vol.
2BORPD—Bitwise Logical OR of Double-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, N-ZReal-Address Mode Exceptions#GP(0)If a memory operand is not aligned on a 16-byte boundary,regardless of segment.If any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.Compatibility Mode ExceptionsSame as for protected mode exceptions.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.If memory operand is not aligned on a 16-byte boundary,regardless of segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.ORPD—Bitwise Logical OR of Double-Precision Floating-Point ValuesVol.
2B 4-13INSTRUCTION SET REFERENCE, N-ZORPS—Bitwise Logical OR of Single-Precision Floating-Point ValuesOpcodeInstruction64-BitModeCompat/Leg ModeDescription0F 56 /rORPS xmm1, xmm2/m128ValidValidBitwise OR ofxmm2/m128 andxmm1.DescriptionPerforms a bitwise logical OR of the four packed single-precision floating-point valuesfrom the source operand (second operand) and the destination operand (firstoperand), and stores the result in the destination operand. The source operand canbe an XMM register or a 128-bit memory location. The destination operand is an XMMregister.In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction toaccess additional registers (XMM8-XMM15).OperationDEST[127:0] ← DEST[127:0] BitwiseOR SRC[127:0];Intel C/C++ Compiler Intrinsic EquivalentORPS__m128 _mm_or_ps(__m128 a, __m128 b)SIMD Floating-Point ExceptionsNone.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.4-14 Vol.
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