Volume 3B System Programming Guide_ Part 2 (794104), страница 95
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(R/W)Set to disable (default); clear toenable.3Address/Request Error CheckingDisable. (R/W)Set to disable (default); clear toenable.4Initiator MCERR# Disable. (R/W)Set to disable MCERR# driving forinitiator bus requests (default);clear to enable.5Internal MCERR# Disable.
(R/W)Set to disable MCERR# driving forinitiator internal errors (default);clear to enable.6BINIT# Driver Disable. (R/W)Set to disable BINIT# driver(default); clear to enable driver.63:72CH44MSR_EBC_FREQUENCY_IDReserved.2,3, 4,6SharedProcessor FrequencyConfiguration.The bit field layout of this MSRvaries according to the MODELvalue in the CPUID versioninformation.
The following bit fieldlayout applies to Pentium 4 andXeon Processors with MODELencoding equal or greater than 2.(R) The field Indicates the currentprocessor frequency configuration.B-30 Vol. 3MODEL-SPECIFIC REGISTERS (MSRS)Table B-2. MSRs in the Pentium 4 and Intel Xeon Processors (Contd.)RegisterAddressHexRegister NameFields and FlagsDecModelAvailabilityShared/Unique1Bit Description15:0Reserved.18:16Scalable Bus Speed. (R/W)Indicates the intended scalablebus speed:Encoding000B000B001B010B011B100BScalable Bus Speed100 MHz (Model 2)266 MHz (Model 3 or 4)133 MHz200 MHz166 MHz333 MHz (Model 6)133.33 MHz should be utilized ifperforming calculation withSystem Bus Speed when encodingis 001B.166.67 MHz should be utilized ifperforming calculation withSystem Bus Speed when encodingis 011B.266.67 MHz should be utilized ifperforming calculation withSystem Bus Speed when encodingis 000B and model encoding = 3or 4.333.33 MHz should be utilized ifperforming calculation withSystem Bus Speed when encodingis 100B and model encoding = 6.All other values are reserved.23:19Reserved31:24Core Clock Frequency to SystemBus Frequency Ratio.
(R)The processor core clockfrequency to system busfrequency ratio observed at thede-assertion of the reset pin.63:25Reserved.Vol. 3 B-31MODEL-SPECIFIC REGISTERS (MSRS)Table B-2. MSRs in the Pentium 4 and Intel Xeon Processors (Contd.)RegisterAddressHexDec2CH44Register NameFields and FlagsMSR_EBC_FREQUENCY_IDModelAvailabilityShared/Unique10, 1SharedBit DescriptionProcessor FrequencyConfiguration. (R)The bit field layout of this MSRvaries according to the MODELvalue of the CPUID versioninformation.
This bit field layoutapplies to Pentium 4 and XeonProcessors with MODEL encodingless than 2.Indicates current processorfrequency configuration.20:0Reserved.23:21Scalable Bus Speed. (R/W)Indicates the intended scalablebus speed:Encoding Scalable Bus Speed000B100 MHzAll others values reserved.63:243AH58IA32_FEATURE_CONTROLReserved.3, 4, 6UniqueControl Features in IA-32Processor. (R/W)(If CPUID.01H:ECX.[bit 5])79H121IA32_BIOS_UPDT_TRIG0, 1, 2,3, 4, 6SharedBIOS Update Trigger Register.(R/W)Executing a WRMSR instruction tothis MSR causes a microcodeupdate to be loaded into theprocessor.
See Section 9.11.6,“Microcode Update Loader.”A processor may prevent writingto this MSR when loading gueststates on VM entries or savingguest states on VM exits.B-32 Vol. 3MODEL-SPECIFIC REGISTERS (MSRS)Table B-2. MSRs in the Pentium 4 and Intel Xeon Processors (Contd.)RegisterAddressHexDec8BH139Register NameFields and FlagsModelAvailabilityShared/Unique1IA32_BIOS_SIGN_ID0, 1, 2,3, 4, 6UniqueBit DescriptionBIOS Update Signature ID.
(R/W)Returns the microcode updatesignature following the executionof CPUID.01H.A processor may prevent writingto this MSR when loading gueststates on VM entries or savingguest states on VM exits.31:0Reserved.63:32Microcode Update Signature.(R/W)It is recommended that this fieldbe pre-loaded with 0 prior toexecuting CPUID.If the field remains 0 following theexecution of CPUID; this indicatesthat no microcode update isloaded.
Any non-zero value is themicrocode update signature.9BH155IA32_SMM_MONITOR_CTL3, 4, 6UniqueSMM Monitor Configuration.(R/W).(If CPUID.1.ECX.[bit 9] andIA32_VMX_BASIC[bit 49];writeable only in SMM)FEH174H254372IA32_MTRRCAPIA32_SYSENTER_CS0, 1, 2,3, 4, 6Unique0, 1, 2,3, 4, 6UniqueMTRR Information.See Section 10.11.1, “MTRRFeature Identification.”.CS register target for CPL 0code. (R/W)Used by SYSENTER and SYSEXITinstructions.
See Section 4.8.7,“Performing Fast Calls to SystemProcedures with the SYSENTERand SYSEXIT Instructions.”Vol. 3 B-33MODEL-SPECIFIC REGISTERS (MSRS)Table B-2. MSRs in the Pentium 4 and Intel Xeon Processors (Contd.)RegisterAddressHexDec175H373Register NameFields and FlagsIA32_SYSENTER_ESPModelAvailabilityShared/Unique10, 1, 2,3, 4, 6UniqueBit DescriptionStack pointer for CPL 0 stack.(R/W)Used by SYSENTER and SYSEXITinstructions. See Section 4.8.7,“Performing Fast Calls to SystemProcedures with the SYSENTERand SYSEXIT Instructions.”176H179H17AH17BH374377378379IA32_SYSENTER_EIPIA32_MCG_CAPIA32_MCG_STATUS0, 1, 2,3, 4, 6Unique0, 1, 2,3, 4, 6Unique0, 1, 2,3, 4, 6UniqueCPL 0 code entry point.
(R/W)Used by SYSENTER and SYSEXITinstructions. See Section 4.8.7,“Performing Fast Calls to SystemProcedures with the SYSENTERand SYSEXIT Instructions.”Machine Check Capabilities. (R)Returns the capabilities of themachine check architecture for theprocessor. See Section 14.3.1.1,“IA32_MCG_CAP MSR.”Machine Check Status.
(R)Returns machine check statefollowing the generation of amachine check exception. SeeSection 14.3.1.2,“IA32_MCG_STATUS MSR.”IA32_MCG_CTLMachine Check Feature Enable.(R/W)Enables machine check capability.See Section 14.3.1.3,“IA32_MCG_CTL MSR.”180H384IA32_MCG_RAX0, 1, 2,3, 4, 6UniqueMachine Check EAX/RAX SaveState.See Section 14.3.2.5, “IA32_MCGExtended Machine Check StateMSRs.”B-34 Vol. 3MODEL-SPECIFIC REGISTERS (MSRS)Table B-2. MSRs in the Pentium 4 and Intel Xeon Processors (Contd.)RegisterAddressHexRegister NameFields and FlagsDecModelAvailabilityShared/Unique163:0181H385IA32_MCG_RBXBit DescriptionContains register state at time ofmachine check error.
When in non64-bit modes at the time of theerror, bits 63-32 do not containvalid data.0, 1, 2,3, 4, 6UniqueMachine Check EBX/RBX SaveState.See Section 14.3.2.5, “IA32_MCGExtended Machine Check StateMSRs.”63:0182H386IA32_MCG_RCXContains register state at time ofmachine check error. When in non64-bit modes at the time of theerror, bits 63-32 do not containvalid data.0, 1, 2,3, 4, 6UniqueMachine Check ECX/RCX SaveState.See Section 14.3.2.5, “IA32_MCGExtended Machine Check StateMSRs.”63:0183H387IA32_MCG_RDXContains register state at time ofmachine check error. When in non64-bit modes at the time of theerror, bits 63-32 do not containvalid data.0, 1, 2,3, 4, 6UniqueMachine Check EDX/RDX SaveState.See Section 14.3.2.5, “IA32_MCGExtended Machine Check StateMSRs.”63:0Contains register state at time ofmachine check error.
When in non64-bit modes at the time of theerror, bits 63-32 do not containvalid data.Vol. 3 B-35MODEL-SPECIFIC REGISTERS (MSRS)Table B-2. MSRs in the Pentium 4 and Intel Xeon Processors (Contd.)RegisterAddressHexDec184H388Register NameFields and FlagsIA32_MCG_RSIModelAvailabilityShared/Unique10, 1, 2,3, 4, 6UniqueBit DescriptionMachine Check ESI/RSI SaveState.See Section 14.3.2.5, “IA32_MCGExtended Machine Check StateMSRs.”63:0185H389IA32_MCG_RDIContains register state at time ofmachine check error.
When in non64-bit modes at the time of theerror, bits 63-32 do not containvalid data.0, 1, 2,3, 4, 6UniqueMachine Check EDI/RDI SaveState.See Section 14.3.2.5, “IA32_MCGExtended Machine Check StateMSRs.”63:0186H390IA32_MCG_RBPContains register state at time ofmachine check error. When in non64-bit modes at the time of theerror, bits 63-32 do not containvalid data.0, 1, 2,3, 4, 6UniqueMachine Check EBP/RBP SaveState.See Section 14.3.2.5, “IA32_MCGExtended Machine Check StateMSRs.”63:0187H391IA32_MCG_RSPContains register state at time ofmachine check error.
When in non64-bit modes at the time of theerror, bits 63-32 do not containvalid data.0, 1, 2,3, 4, 6UniqueMachine Check ESP/RSP SaveState.See Section 14.3.2.5, “IA32_MCGExtended Machine Check StateMSRs.”B-36 Vol. 3MODEL-SPECIFIC REGISTERS (MSRS)Table B-2. MSRs in the Pentium 4 and Intel Xeon Processors (Contd.)RegisterAddressHexRegister NameFields and FlagsDecModelAvailabilityShared/Unique163:0188H392IA32_MCG_RFLAGSBit DescriptionContains register state at time ofmachine check error. When in non64-bit modes at the time of theerror, bits 63-32 do not containvalid data.0, 1, 2,3, 4, 6UniqueMachine Check EFLAGS/RFLAGSave State.See Section 14.3.2.5, “IA32_MCGExtended Machine Check StateMSRs.”63:0189H393IA32_MCG_RIPContains register state at time ofmachine check error.
When in non64-bit modes at the time of theerror, bits 63-32 do not containvalid data.0, 1, 2,3, 4, 6UniqueMachine Check EIP/RIP SaveState.See Section 14.3.2.5, “IA32_MCGExtended Machine Check StateMSRs.”63:018AH394IA32_MCG_MISCContains register state at time ofmachine check error. When in non64-bit modes at the time of theerror, bits 63-32 do not containvalid data.0, 1, 2,3, 4, 6UniqueMachine Check Miscellaneous.See Section 14.3.2.5, “IA32_MCGExtended Machine Check StateMSRs.”Vol. 3 B-37MODEL-SPECIFIC REGISTERS (MSRS)Table B-2. MSRs in the Pentium 4 and Intel Xeon Processors (Contd.)RegisterAddressHexRegister NameFields and FlagsDecModelAvailabilityShared/Unique10Bit DescriptionDS.When set, the bit indicates that apage assist or page fault occurredduring DS normal operation.
Theprocessors response is to shutdown.The bit is used as an aid fordebugging DS handling code. It isthe responsibility of the user (BIOSor operating system) to clear thisbit for normal operation.63:1Reserved.18BH395IA32_MCG_RESERVED1Reserved.18CH396IA32_MCG_RESERVED2Reserved.18DH397IA32_MCG_RESERVED3Reserved.18EH398IA32_MCG_RESERVED4Reserved.18FH399IA32_MCG_RESERVED5Reserved.190H400IA32_MCG_R863-0B-38 Vol.
30, 1, 2,3, 4, 6UniqueMachine Check R8.See Section 14.3.2.5, “IA32_MCGExtended Machine Check StateMSRs.”Registers R8-15 (and theassociated state-save MSRs) existonly in Intel 64 processors. Theseregisters contain valid informationonly when the processor isoperating in 64-bit mode at thetime of the error.MODEL-SPECIFIC REGISTERS (MSRS)Table B-2.
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