Volume 3B System Programming Guide_ Part 2 (794104), страница 92
Текст из файла (страница 92)
(R/W)0Fast-Strings Enable.Allows a variety of processor functions to beenabled and disabled.When set, the fast-strings feature (for REPMOVS and REP STORS) is enabled (default);when clear, fast-strings are disabled.2:13Reserved.UniqueAutomatic Thermal Control Circuit Enable.(R/W)1 = Setting this bit enables the thermalcontrol circuit (TCC) portion of the IntelThermal Monitor feature. This allowsprocessor clocks to be automaticallymodulated based on the processor'sthermal sensor operation.0 = Disabled (default).The automatic thermal control circuit enablebit determines if the thermal control circuit(TCC) will be activated when the processor'sinternal thermal sensor determines theprocessor is about to exceed its maximumoperating temperature.When the TCC is activated and TM1 is enabled,processors clocks are forced to a 50% dutycycle.
BIOS must enable this feature.Do not confuse the bit with the on-demandthermal control circuit enable bit.6:47Reserved.SharedPerformance Monitoring Available. (R)1=0=8Performance monitoring enabledPerformance monitoring disabledReserved.Vol. 3 B-11MODEL-SPECIFIC REGISTERS (MSRS)Table B-1. MSRs in Processors Based on Intel Core Microarchitecture (Contd.)RegisterAddressHexRegister NameShared/UniqueBit DescriptionDec9Hardware Prefetcher Disable.
(R/W)When set, disables the hardware prefetcheroperation on streams of data. When clear(default), enables the prefetch queue.Disabling of the hardware prefetcher mayimpact processor performance.10SharedFERR# Multiplexing Enable. (R/W)1=FERR# asserted by the processor toindicate a pending break event withinthe processor0 = Indicates compatible FERR# signalingbehaviorThis bit must be set to 1 to support XAPICinterrupt model usage.11SharedBranch Trace Storage Unavailable. (RO)1=0=12SharedProcessor doesn’t support branch tracestorage (BTS)BTS is supportedPrecise Event Based Sampling Unavailable.(RO)1=Processor does not support preciseevent-based sampling (PEBS);0 = PEBS is supported.The Intel Core Solo and Intel Core Duoprocessors do not support PEBS.13SharedTM2 Enable.
(R/W)When this bit is set (1) and the thermal sensorindicates that the die temperature is at thepre-determined threshold, the ThermalMonitor 2 mechanism is engaged. TM2 willreduce the bus to core ratio and voltageaccording to the value last written toMSR_THERM2_CTL bits 15:0.B-12 Vol. 3MODEL-SPECIFIC REGISTERS (MSRS)Table B-1. MSRs in Processors Based on Intel Core Microarchitecture (Contd.)RegisterAddressHexRegister NameShared/UniqueBit DescriptionDecWhen this bit is clear (0, default), theprocessor does not change the VID signals orthe bus to core ratio when the processorenters a thermally managed state.The BIOS must enable this feature if the TM2feature flag (CPUID.1:ECX[8]) is set; if the TM2feature flag is not set, this feature is notsupported and BIOS must not alter thecontents of the TM2 bit location.The processor is operating out of specificationif both this bit and the TM1 bit are set to 0.15:1416Reserved.SharedEnhanced Intel SpeedStep TechnologyEnable.
(R/W)0=Enhanced Intel SpeedStep Technologydisabled1 = Enhanced Intel SpeedStep Technologyenabled18SharedENABLE MONITOR FSM. (R/W)When this bit is set to 0, the MONITOR featureflag is not set (CPUID.01H:ECX[bit 3] = 0). Thisindicates that MONITOR/MWAIT are notsupported. An Illegal Instruction exception isgenerated if software attempts to executeMONITOR/MWAIT when this bit is 0.When this bit is set to 1 (default),MONITOR/MWAIT are supported(CPUID.01H:ECX[bit 3] = 1).If the SSE3 feature flag ECX[0] is not set(CPUID.01H:ECX[bit 0] = 0), the OS must notattempt to alter this bit. BIOS must leave it inthe default state.
Writing this bit when theSSE3 feature flag is set to 0 may generate a#GP exception.Vol. 3 B-13MODEL-SPECIFIC REGISTERS (MSRS)Table B-1. MSRs in Processors Based on Intel Core Microarchitecture (Contd.)RegisterAddressHexRegister NameShared/UniqueBit DescriptionDec19SharedAdjacent Cache Line Prefetch Disable.(R/W)When set to 1, the processor fetches thecache line that contains data currentlyrequired by the processor. When set to 0, theprocessor fetches cache lines that comprise acache line pair (128 bytes).Single processor platforms should not set thisbit. Server platforms should set or clear thisbit based on platform performance observedin validation and testing.BIOS may contain a setup option that controlsthe setting of this bit.20SharedEnhanced Intel SpeedStep TechnologySelect Lock. (R/WO)When set, this bit causes the following bits tobecome read-only:• Enhanced Intel SpeedStep TechnologySelect Lock (this bit),• Enhanced Intel SpeedStep TechnologyEnable bit.The bit must be set before an Enhanced IntelSpeedStep Technology transition is requested.This bit is cleared on reset.2122Reserved.SharedLimit CPUID Maxval.
(R/W)When this bit is set to 1, CPUID.00H returns amaximum value in EAX[7:0] of 3. When set toa 0 (default), CPUID.00H returns the numberof the maximum standard function supportedin EAX[7:0].BIOS should contain a setup question thatallows users to specify when the installed OSdoes not support CPUID functions greaterthan 3.B-14 Vol. 3MODEL-SPECIFIC REGISTERS (MSRS)Table B-1. MSRs in Processors Based on Intel Core Microarchitecture (Contd.)RegisterAddressHexRegister NameShared/UniqueBit DescriptionDecBefore setting this bit, BIOS must execute theCPUID.01H and examine the maximum valuereturned in EAX[7:0].
If the maximum value isgreater than 3, the bit is supported.Otherwise, the bit is not supported. Writing tothis bit when the maximum value is greaterthan 3 may generate a #GP exception.Setting this bit may cause behavior insoftware that depends on the availability ofCPUID leaves greater than 3.23SharedxTPR Message Disable. (R/W)When set to 1, xTPR messages are disabled.xTPR messages are optional messages thatallow the processor to inform the chipset ofits priority.33:2434Reserved.UniqueXD Bit Disable. (R/W)When set to 1, the Execute Disable Bit feature(XD Bit) is disabled and the XD Bit extendedfeature flag will be clear (CPUID.80000001H:EDX[20]=0).When set to a 0 (default), the Execute DisableBit feature (if available) allows the OS toenable PAE paging and take advantage of dataonly pages.Assuming this bit is not set to 1 and ifCPUID.80000001H:EDX[20]=0, this feature isnot supported and BIOS must not alter thecontents of this bit location.
Writing this bit to1 when the XD Bit extended feature flag isset to 0 may generate a #GP exception.36:35Reserved.Vol. 3 B-15MODEL-SPECIFIC REGISTERS (MSRS)Table B-1. MSRs in Processors Based on Intel Core Microarchitecture (Contd.)RegisterAddressHexRegister NameShared/UniqueBit DescriptionDec37UniqueDCU Prefetcher Disable. (R/W)When set to 1, The DCU L1 data cacheprefetcher is disabled. The default value afterreset is 0.
BIOS may write ‘1’ to disable thisfeature.The DCU prefetcher is an L1 data cacheprefetcher. When the DCU prefetcher detectsmultiple loads from the same line done withina time limit, the DCU prefetcher assumes thenext line will be required. The next line isprefetched in to the L1 data cache frommemory or L2.38SharedIDA Disable.
(R/W)When set to 1 on processors that support IDA,the Intel Dynamic Acceleration feature (IDA) isdisabled and the IDA_Enable feature flag willbe clear (CPUID.06H: EAX[1]=0).When set to a 0 on processors that supportIDA, CPUID.06H: EAX[1] reports theprocessor’s support of IDA is enabled.Note: the power-on default value is used byBIOS to detect hardware support of IDA. Ifpower-on default value is 1, IDA is available inthe processor. If power-on default value is 0,IDA is not available.39UniqueIP Prefetcher Disable. (R/W)When set to 1, The IP prefetcher is disabled.The default value after reset is 0. BIOS maywrite ‘1’ to disable this feature.The IP prefetcher is an L1 data cacheprefetcher.
The IP prefetcher looks forsequential load history to determine whetherto prefetch the next expected data into theL1 cache from memory or L2.63:40B-16 Vol. 3Reserved.MODEL-SPECIFIC REGISTERS (MSRS)Table B-1. MSRs in Processors Based on Intel Core Microarchitecture (Contd.)RegisterAddressHexDec1C9H457Register NameMSR_LASTBRANCH_TOSShared/UniqueUniqueBit DescriptionLast Branch Record Stack TOS.
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