Volume 3B System Programming Guide_ Part 2 (794104), страница 90
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Note that duringthe time that the processor isexecuting the HLT instruction, theTime-Stamp Counter is not disabled.Since this event is controlled by theCounter Controls CC0, CC1 it can beused to calculate the CPI at CPL=3,which the TSC cannot provide.30HDATA_CACHE_TLB_MISS_STALL_DURATION(Counter 1)Number of clocks thepipeline is stalled due toa data cache translationlook-aside buffer (TLB)miss31HMMX_INSTRUCTION_DATA_READS(Counter 0)Number of MMXinstruction data reads31HMMX_INSTRUCTION_DATA_READ_MISSES(Counter 1)Number of MMXinstruction data readmisses32HFLOATING_POINT_S Number of clocks whileTALLS_DURATIONpipe is stalled due to a(Counter 0)floating-point freezeVol. 3 A-133PERFORMANCE-MONITORING EVENTSTable A-15.
Events That Can Be Counted with Pentium ProcessorPerformance-Monitoring Counters (Contd.)EventNum.Mnemonic EventNameDescriptionComments32HTAKEN_BRANCHES(Counter 1)Number of takenbranches33HD1_STARVATION_AND_FIFO_IS_EMPTY(Counter 0)Number of times D1stage cannot issue ANYinstructions since theFIFO buffer is emptyThe D1 stage can issue 0, 1, or 2instructions per clock if those areavailable in an instructions FIFObuffer.33HD1_STARVATION_AND_ONLY_ONE_INSTRUCTION_IN_FIFO(Counter 1)Number of times the D1stage issues a singleinstruction (since theFIFO buffer had just oneinstruction ready)The D1 stage can issue 0, 1, or 2instructions per clock if those areavailable in an instructions FIFObuffer.34HMMX_INSTRUCTION_DATA_WRITES(Counter 0)Number of data writescaused by MMXinstructions34HMMX_INSTRUCTION_DATA_WRITE_MISSES(Counter 1)Number of data writemisses caused by MMXinstructionsA-134 Vol.
3When combined with the previouslydefined events, Instruction Executed(16H) and Instruction Executed inthe V-pipe (17H), this event enablesthe user to calculate the numbers oftime pairing rules prevented issuingof two instructions.PERFORMANCE-MONITORING EVENTSTable A-15. Events That Can Be Counted with Pentium ProcessorPerformance-Monitoring Counters (Contd.)EventNum.35HMnemonic EventNamePIPELINE_FLUSHES_DUE_TO_WRONG_BRANCH_PREDICTIONS(Counter 0)DescriptionCommentsNumber of pipelineflushes due to wrongbranch predictionsresolved in either the Estage or the WB-stageThe count includes any pipeline flushdue to a branch that the pipeline didnot follow correctly. It includes caseswhere a branch was not in the BTB,cases where a branch was in the BTBbut was mispredicted, and caseswhere a branch was correctlypredicted but to the wrong address.Branches are resolved in either theExecute stage (E-stage) or theWriteback stage (WB-stage). In thelater case, the misprediction penaltyis larger by one clock.
The differencebetween the 35H event count incounter 0 and counter 1 is thenumber of E-stage resolvedbranches.35HPIPELINE_FLUSHES_DUE_TO_WRONG_BRANCH_PREDICTIONS_RESOLVED_IN_WB-STAGE(Counter 1)Number of pipelineflushes due to wrongbranch predictionsresolved in the WBstage36HMISALIGNED_DATA_MEMORY_REFERENCE_ON_MMX_INSTRUCTIONS(Counter 0)Number of misaligneddata memory referenceswhen executing MMXinstructions36HPIPELINE_ISTALL_FOR_MMX_INSTRUCTION_DATA_MEMORY_READS(Counter 1)Number clocks duringpipeline stalls caused bywaits form MMXinstruction data memoryreadsSee note for event 35H (Counter 0).T3:Vol.
3 A-135PERFORMANCE-MONITORING EVENTSTable A-15. Events That Can Be Counted with Pentium ProcessorPerformance-Monitoring Counters (Contd.)EventNum.Mnemonic EventNameDescriptionComments37HMISPREDICTED_OR_UNPREDICTED_RETURNS(Counter 1)Number of returnspredicted incorrectly ornot predicted at allThe count is the difference betweenthe total number of executed returnsand the number of returns that werecorrectly predicted.
Only RETinstructions are counted (forexample, IRET instructions are notcounted).37HPREDICTED_RETURNS(Counter 1)Number of predictedreturns (whether theyare predicted correctlyand incorrectlyOnly RET instructions are counted(for example, IRET instructions arenot counted).38HMMX_MULTIPLY_UNIT_INTERLOCK(Counter 0)Number of clocks thepipe is stalled since thedestination of previousMMX multiplyinstruction is not readyyetThe counter will not be incrementedif there is another cause for a stall.For each occurrence of a multiplyinterlock, this event will be countedtwice (if the stalled instructioncomes on the next clock after themultiply) or by once (if the stalledinstruction comes two clocks afterthe multiply).38HMOVD/MOVQ_STORE_STALL_DUE_TO_PREVIOUS_MMX_OPERATION(Counter 1)Number of clocks aMOVD/MOVQ instructionstore is stalled in D2stage due to a previousMMX operation with adestination to be used inthe store instruction.39HRETURNS(Counter 0)Number or returnsexecuted.39HReservedA-136 Vol.
3Only RET instructions are counted;IRET instructions are not counted.Any exception taken on a RETinstruction and any interruptrecognized by the processor on theinstruction boundary prior to theexecution of the RET instruction willalso cause this counter to beincremented.PERFORMANCE-MONITORING EVENTSTable A-15. Events That Can Be Counted with Pentium ProcessorPerformance-Monitoring Counters (Contd.)EventNum.Mnemonic EventNameDescription3AHBTB_FALSE_ENTRIES(Counter 0)Number of false entriesin the Branch TargetBuffer3AHBTB_MISS_PREDICTION_ON_NOT-TAKEN_BRANCH(Counter 1)Number of times theBTB predicted a nottaken branch as taken3BHFULL_WRITE_BUFFER_STALL_DURATION_WHILE_EXECUTING_MMX_INSTRUCTIONS(Counter 0)Number of clocks whilethe pipeline is stalleddue to full write bufferswhile executing MMXinstructions3BHSTALL_ON_MMX_INSTRUCTION_WRITE_TO E-_OR_M-STATE_LINE(Counter 1)Number of clocks duringstalls on MMXinstructions writing toE- or M-state linesCommentsFalse entries are causes formisprediction other than a wrongprediction.Vol.
3 A-137PERFORMANCE-MONITORING EVENTSA-138 Vol. 3APPENDIX BMODEL-SPECIFIC REGISTERS (MSRS)This appendix lists MSRs provided in Intel Core 2 processor family, Intel Core Duo,Intel Core Solo, Pentium 4 and Intel Xeon processors, P6 family processors, andPentium processors in Tables B-2, B-7, and B-8, respectively. All MSRs listed can beread with the RDMSR and written with the WRMSR instructions.Register addresses are given in both hexadecimal and decimal.
The register name isthe mnemonic register name and the bit description describes individual bits inregisters.Table B-9 lists the architectural MSRs.B.1MSRS IN THE INTEL® CORE™ 2 PROCESSOR FAMILYModel-specific registers (MSRs) for Intel Core 2 processor family and for Intel Xeonprocessors based on Intel Core microarchitecture are listed in Table B-1. The column“Shared/Unique” applies to multi-core processors based on Intel Core microarchitecture.
“Unique” means each processor core has a separate MSR, or a bit field in anMSR governs only a core independently. “Shared” means the MSR or the bit field inan MSR address governs the operation of both processor cores.Table B-1. MSRs in Processors Based on Intel Core MicroarchitectureRegisterAddressRegister NameShared/UniqueBit DescriptionHexDec0H0IA32_P5_MC_ADDRUniqueSee Appendix B.6, “MSRs in PentiumProcessors.”1H1IA32_P5_MC_TYPEUniqueSee Appendix B.6, “MSRs in PentiumProcessors.”6H6IA32_MONITOR_FILTER_SIZEUniqueSee Section 7.11.5, “Monitor/Mwait AddressRange Determination.”10H16IA32_TIME_STAMP_COUNTERUniqueSee Section 18.10, “Time-Stamp Counter.”17H23IA32_PLATFORM_IDSharedPlatform ID.
(R)The operating system can use this MSR todetermine “slot” information for the processorand the proper microcode update to load.49:0Reserved.Vol. 3 B-1MODEL-SPECIFIC REGISTERS (MSRS)Table B-1. MSRs in Processors Based on Intel Core Microarchitecture (Contd.)RegisterAddressHexRegister NameShared/UniqueBit DescriptionDec52:50Platform Id. (R)Contains information concerning the intendedplatform for the processor.520000111163:5317H23MSR_PLATFORM_ID51001100115001010101Processor Flag 0Processor Flag 1Processor Flag 2Processor Flag 3Processor Flag 4Processor Flag 5Processor Flag 6Processor Flag 7Reserved.Unique7:0See Section 8.4.4, “Local APIC Status andLocation.”Reserved.12:8Maximum Qualified Ratio. (R)The maximum allowed bus ratio.63:13Reserved.1BH27IA32_APIC_BASEUniqueSee Section 8.4.4, “Local APIC Status andLocation.”2AH42MSR_EBL_CR_POWERONSharedProcessor Hard Power-On Configuration.(R/W)Enables and disables processor features; (R)indicates current processor configuration.0Reserved1Data Error Checking Enable.
(R/W)1 = Enabled0 = DisabledAlways 0 on the Pentium M processor.2Response Error Checking Enable. (R/W)FRCERR Observation Enable:1 = Enabled0 = DisabledAlways 0 on the Pentium M processor.B-2 Vol. 3MODEL-SPECIFIC REGISTERS (MSRS)Table B-1. MSRs in Processors Based on Intel Core Microarchitecture (Contd.)RegisterAddressHexRegister NameShared/UniqueBit DescriptionDec3AERR# Drive Enable. (R/W)1 = Enabled0 = DisabledAlways 0 on the Pentium M processor.4BERR# Enable for initiator bus requests.(R/W)1 = Enabled0 = DisabledAlways 0 on the Pentium M processor.5Reserved6BERR# Driver Enable for initiator internalerrors. (R/W)1 = Enabled0 = DisabledAlways 0 on the Pentium M processor.7BINIT# Driver Enable.
(R/W)1 = Enabled0 = DisabledAlways 0 on the Pentium M processor.8Output Tri-state Enabled. (R/O)1 = Enabled0 = Disabled9Execute BIST. (R/O)1 = Enabled0 = Disabled10AERR# Observation Enabled. (R/O)1 = Enabled0 = DisabledAlways 0 on the Pentium M processor.11ReservedVol. 3 B-3MODEL-SPECIFIC REGISTERS (MSRS)Table B-1. MSRs in Processors Based on Intel Core Microarchitecture (Contd.)RegisterAddressHexRegister NameShared/UniqueBit DescriptionDec12BINIT# Observation Enabled.
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