Volume 3B System Programming Guide_ Part 2 (794104), страница 94
Текст из файла (страница 94)
(R/O)See Appendix G.7, “VMX-Fixed Bits in CR4”(If CPUID.01H:ECX.[bit 9])489H1161IA32_VMX_CR4_FI UniqueXED1Capability Reporting Register of CR4 BitsFixed to 1. (R/O)See Appendix G.7, “VMX-Fixed Bits in CR4”(If CPUID.01H:ECX.[bit 9])48AH1162IA32_VMX_VMCS_ENUMUniqueCapability Reporting Register of VMCS FieldEnumeration. (R/O).See Appendix G.8, “VMCS Enumeration”(If CPUID.01H:ECX.[bit 9])48BH1163IA32_VMX_PROCB UniqueASED_CTLS2Capability Reporting Register of SecondaryProcessor-based VM-execution Controls.(R/O)See Appendix G.2, “VM-Execution Controls”(If CPUID.01H:ECX.[bit 9] andIA32_VMX_PROCBASED_CTLS[bit 63])600H1536IA32_DS_AREAUniqueDS Save Area. (R/W)Points to the DS buffer management area,which is used to manage the BTS and PEBSbuffers.See Section 18.15.4, “Debug Store (DS)Mechanism.”31:0DS Buffer Management Area.Linear address of the first byte of the DSbuffer management area.63:32C000_0080HIA32_EFERReserved.UniqueVol.
3 B-23MODEL-SPECIFIC REGISTERS (MSRS)Table B-1. MSRs in Processors Based on Intel Core Microarchitecture (Contd.)RegisterAddressHexRegister NameShared/UniqueBit DescriptionDec0SYSCALL Enable. (R/W)Enables SYSCALL/SYSRET instructions in 64bit mode.7:1Reserved.8IA-32e Mode Enable.
(R/W)Enables IA-32e mode operation.9Reserved.10IA-32e Mode Active. (R)Indicates IA-32e mode is active when set.11Execute Disable Bit Enable.63:12ReservedC000_0081HIA32_STARC000_0082HIA32_LSTARUniqueSystem Call Target Address. (R/W)(If CPUID.80000001.EDX.[bit 29])UniqueIA-32e Mode System Call Target Address.(R/W)(If CPUID.80000001.EDX.[bit 29])C000_0084HIA32_FMASKC000_0100HIA32_FS_BASEC000_0101HIA32_GS_BASEC000_0102HIA32_KERNEL_GSBASEB-24 Vol. 3UniqueSystem Call Flag Mask.
(R/W)(If CPUID.80000001.EDX.[bit 29])UniqueMap of BASE Address of FS. (R/W)(If CPUID.80000001.EDX.[bit 29])UniqueMap of BASE Address of GS. (R/W)(If CPUID.80000001.EDX.[bit 29])UniqueSwap Target of BASE Address of GS. (R/W)(If CPUID.80000001.EDX.[bit 29])MODEL-SPECIFIC REGISTERS (MSRS)B.2MSRS IN THE PENTIUM® 4 AND INTEL® XEON®PROCESSORSThe following MSRs are defined for the Pentium 4 and Intel Xeon processors based onIntel NetBurst microarchitecture:•MSRs with an “IA32_” prefix are designated as “architectural.” This means thatthe functions of these MSRs and their addresses remain the same for succeedingfamilies of IA-32 processors.•MSRs with an “MSR_” prefix are model specific with respect to address functionalities. The column “Model Availability” lists the model encoding value(s) withinthe Pentium 4 and Intel Xeon processor family at the specified register address.The model encoding value of a processor can be queried using CPUID.
See“CPUID—CPU Identification” in Chapter 3 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A.Table B-2. MSRs in the Pentium 4 and Intel Xeon ProcessorsRegisterAddressRegister NameFields and FlagsModelAvailabilityShared/Unique1Bit DescriptionHexDec0H0IA32_P5_MC_ADDR0, 1, 2,3, 4, 6SharedSee Appendix B.6, “MSRs inPentium Processors.”1H1IA32_P5_MC_TYPE0, 1, 2,3, 4, 6SharedSee Appendix B.6, “MSRs inPentium Processors.”6H6IA32_MONITOR_FILTER_LINE_SIZE3, 4, 6SharedSee Section 7.11.5,“Monitor/Mwait Address RangeDetermination.”15:0Monitor filter line size.
(R/W)Specifies the number of bytes in acache line or chipset line buffer. Avalue of 40H (default) specifies asize of 64 bytes.This register field is used tospecify the size of the semaphorespacing and alignment for theMONITOR and MWAIT instructions.BIOS reads this field and thechipset line buffer register. BIOSthen programs this register fieldwith the larger of the two values.63:16Reserved.Vol. 3 B-25MODEL-SPECIFIC REGISTERS (MSRS)Table B-2. MSRs in the Pentium 4 and Intel Xeon Processors (Contd.)RegisterAddressHexDec10H16Register NameFields and FlagsModelAvailabilityShared/Unique1IA32_TIME_STAMP_COUNTER0, 1, 2,3, 4, 6UniqueBit DescriptionTime Stamp Counter.See Section 18.10, “Time-StampCounter.”63:0Timestamp Count Value.A 64-bit register accessed whenreferenced as a qword through aRDMSR, WRMSR or RDTSCinstruction.
Returns the currenttime stamp count value. All 64 bitsare readable.On earlier processors, only thelower 32 bits are writable. On anywrite to the lower 32 bits, theupper 32 bits are cleared. Forprocessor family 0FH, models 3and 4: all 64 bits are writable.17H23IA32_PLATFORM_ID0, 1, 2,3, 4, 6SharedPlatform ID. (R)The operating system can use thisMSR to determine “slot”information for the processor andthe proper microcode update toload.49:0Reserved.52:50Platform Id.
(R)Contains information concerningthe intended platform for theprocessor.520000111163:53B-26 Vol. 351001100115001010101Reserved.Processor Flag 0Processor Flag 1Processor Flag 2Processor Flag 3Processor Flag 4Processor Flag 5Processor Flag 6Processor Flag 7MODEL-SPECIFIC REGISTERS (MSRS)Table B-2. MSRs in the Pentium 4 and Intel Xeon Processors (Contd.)RegisterAddressHexDec1BH27Register NameFields and FlagsIA32_APIC_BASEModelAvailabilityShared/Unique10, 1, 2,3, 4, 6UniqueBit DescriptionAPIC Location and Status.
(R/W)Contains location and statusinformation about the APIC. SeeSection 8.4.4, “Local APIC Statusand Location.”7:0Reserved.8Bootstrap Processor. (BSP)Set if the processor is the BSP.10:9Reserved.11APIC Global Enable.Set if enabled; cleared if disabled.31:12APIC Base Address.The base address of the xAPICmemory map.63:322AH42MSR_EBC_HARD_POWERONReserved.0, 1, 2,3, 4, 6SharedProcessor Hard Power-OnConfiguration.(R/W) Enables and disablesprocessor features; (R) indicatescurrent processor configuration.0Output Tri-state Enabled. (R)Indicates whether tri-state outputis enabled (1) or disabled (0) as setby the strapping of SMI#.
Thevalue in this bit is written on thedeassertion of RESET#; the bit isset to 1 when the address bussignal is asserted.Vol. 3 B-27MODEL-SPECIFIC REGISTERS (MSRS)Table B-2. MSRs in the Pentium 4 and Intel Xeon Processors (Contd.)RegisterAddressHexRegister NameFields and FlagsDec1ModelAvailabilityShared/Unique1Bit DescriptionExecute BIST. (R)Indicates whether the executionof the BIST is enabled (1) ordisabled (0) as set by thestrapping of INIT#.
The value inthis bit is written on thedeassertion of RESET#; the bit isset to 1 when the address bussignal is asserted.2In Order Queue Depth. (R)Indicates whether the in orderqueue depth for the system bus is1 (1) or up to 12 (0) as set by thestrapping of A7#. The value in thisbit is written on the deassertion ofRESET#; the bit is set to 1 whenthe address bus signal is asserted.3MCERR# Observation Disabled.(R)Indicates whether MCERR#observation is enabled (0) ordisabled (1) as determined by thestrapping of A9#. The value in thisbit is written on the deassertion ofRESET#; the bit is set to 1 whenthe address bus signal is asserted.4BINIT# Observation Enabled.
(R)Indicates whether BINIT#observation is enabled (0) ordisabled (1) as determined by thestrapping of A10#. The value inthis bit is written on thedeassertion of RESET#; the bit isset to 1 when the address bussignal is asserted.B-28 Vol. 3MODEL-SPECIFIC REGISTERS (MSRS)Table B-2. MSRs in the Pentium 4 and Intel Xeon Processors (Contd.)RegisterAddressHexRegister NameFields and FlagsDecModelAvailabilityShared/Unique16:5Bit DescriptionAPIC Cluster ID. (R)Contains the logical APIC cluster IDvalue as set by the strapping ofA12# and A11#.
The logicalcluster ID value is written into thefield on the deassertion ofRESET#; the field is set to 1 whenthe address bus signal is asserted.7Bus Park Disable. (R)Indicates whether bus park isenabled (0) or disabled (1) as setby the strapping of A15#. Thevalue in this bit is written on thedeassertion of RESET#; the bit isset to 1 when the address bussignal is asserted.11:8Reserved.13:12Agent ID. (R)Contains the logical agent ID valueas set by the strapping of BR[3:0].The logical ID value is written intothe field on the deassertion ofRESET#; the field is set to 1 whenthe address bus signal is asserted.63:142BH43MSR_EBC_SOFT_POWERONReserved.0, 1, 2,3, 4, 6SharedProcessor Soft Power-OnConfiguration.
(R/W)Enables and disables processorfeatures.0RCNT/SCNT On RequestEncoding Enable. (R/W)Controls the driving of RCNT/SCNTon the request encoding. Set toenable (1); clear to disabled (0,default).Vol. 3 B-29MODEL-SPECIFIC REGISTERS (MSRS)Table B-2. MSRs in the Pentium 4 and Intel Xeon Processors (Contd.)RegisterAddressHexRegister NameFields and FlagsDecModelAvailabilityShared/Unique11Bit DescriptionData Error Checking Disable.(R/W)Set to disable system data busparity checking; clear to enableparity checking.2Response Error CheckingDisable.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
