Volume 3B System Programming Guide_ Part 2 (794104), страница 102
Текст из файла (страница 102)
When not implemented in theprocessor, all reads and writes to this MSR willcause a general-protection exception.404H1028IA32_MC1_CTLUniqueSee Section 14.3.2.1, “IA32_MCi_CTL MSRs.”405H1029IA32_MC1_STATUSUniqueSee Section 14.3.2.2, “IA32_MCi_STATUSMSRS.”B-90 Vol. 3MODEL-SPECIFIC REGISTERS (MSRS)Table B-5. MSRs in Intel Core Solo, Intel Core Duo Processors, and Dual-core IntelXeon Processor LV (Contd.)RegisterAddressHexDec406H1030Register NameIA32_MC1_ADDRShared/UniqueUniqueBit DescriptionSee Section 14.3.2.3, “IA32_MCi_ADDR MSRs.”The IA32_MC1_ADDR register is either notimplemented or contains no address if theADDRV flag in the IA32_MC1_STATUS registeris clear.
When not implemented in theprocessor, all reads and writes to this MSR willcause a general-protection exception.408H1032IA32_MC2_CTLUniqueSee Section 14.3.2.1, “IA32_MCi_CTL MSRs.”409H1033IA32_MC2_STATUSUniqueSee Section 14.3.2.2, “IA32_MCi_STATUSMSRS.”40AH1034IA32_MC2_ADDRUniqueSee Section 14.3.2.3, “IA32_MCi_ADDR MSRs.”The IA32_MC2_ADDR register is either notimplemented or contains no address if theADDRV flag in the IA32_MC2_STATUS registeris clear. When not implemented in theprocessor, all reads and writes to this MSR willcause a general-protection exception.40CH1036MSR_MC4_CTLUniqueSee Section 14.3.2.1, “IA32_MCi_CTL MSRs.”40DH1037MSR_MC4_STATUSUniqueSee Section 14.3.2.2, “IA32_MCi_STATUSMSRS.”40EH1038MSR_MC4_ADDRUniqueSee Section 14.3.2.3, “IA32_MCi_ADDR MSRs.”The MSR_MC4_ADDR register is either notimplemented or contains no address if theADDRV flag in the MSR_MC4_STATUS registeris clear.
When not implemented in theprocessor, all reads and writes to this MSR willcause a general-protection exception.410H1040MSR_MC3_CTLSee Section 14.3.2.1, “IA32_MCi_CTL MSRs.”411H1041MSR_MC3_STATUSSee Section 14.3.2.2, “IA32_MCi_STATUSMSRS.”Vol. 3 B-91MODEL-SPECIFIC REGISTERS (MSRS)Table B-5. MSRs in Intel Core Solo, Intel Core Duo Processors, and Dual-core IntelXeon Processor LV (Contd.)RegisterAddressHexDec412H1042Register NameMSR_MC3_ADDRShared/UniqueUniqueBit DescriptionSee Section 14.3.2.3, “IA32_MCi_ADDR MSRs.”The MSR_MC3_ADDR register is either notimplemented or contains no address if theADDRV flag in the MSR_MC3_STATUS registeris clear. When not implemented in theprocessor, all reads and writes to this MSR willcause a general-protection exception.413H1043MSR_MC3_MISCUnique414H1044MSR_MC5_CTLUnique415H1045MSR_MC5_STATUSUnique416H1046MSR_MC5_ADDRUnique417H1047MSR_MC5_MISCUnique480H1152IA32_VMX_BASICUniqueReporting Register of Basic VMXCapabilities.
(R/O)See Appendix G.1, “Basic VMX Information”(If CPUID.01H:ECX.[bit 9])481H1153IA32_VMX_PINBASED_CTLSUniqueCapability Reporting Register of Pin-basedVM-execution Controls. (R/O)See Appendix G.2, “VM-Execution Controls”(If CPUID.01H:ECX.[bit 9])482H1154IA32_VMX_PROCB UniqueASED_CTLSCapability Reporting Register of PrimaryProcessor-based VM-execution Controls.(R/O)See Appendix G.2, “VM-Execution Controls”(If CPUID.01H:ECX.[bit 9])483H1155IA32_VMX_EXIT_CTLSUniqueCapability Reporting Register of VM-exitControls. (R/O)See Appendix G.3, “VM-Exit Controls”(If CPUID.01H:ECX.[bit 9])B-92 Vol. 3MODEL-SPECIFIC REGISTERS (MSRS)Table B-5.
MSRs in Intel Core Solo, Intel Core Duo Processors, and Dual-core IntelXeon Processor LV (Contd.)RegisterAddressHexDec484H1156Register NameIA32_VMX_ENTRY_CTLSShared/UniqueUniqueBit DescriptionCapability Reporting Register of VM-entryControls. (R/O)See Appendix G.4, “VM-Entry Controls”(If CPUID.01H:ECX.[bit 9])485H1157IA32_VMX_MISCUniqueReporting Register of Miscellaneous VMXCapabilities. (R/O)See Appendix G.5, “Miscellaneous Data”(If CPUID.01H:ECX.[bit 9])486H1158IA32_VMX_CR0_FIXED0UniqueCapability Reporting Register of CR0 BitsFixed to 0.
(R/O)See Appendix G.6, “VMX-Fixed Bits in CR0”(If CPUID.01H:ECX.[bit 9])487H1159IA32_VMX_CR0_FIXED1UniqueCapability Reporting Register of CR0 BitsFixed to 1. (R/O)See Appendix G.6, “VMX-Fixed Bits in CR0”(If CPUID.01H:ECX.[bit 9])488H1160IA32_VMX_CR4_FI UniqueXED0Capability Reporting Register of CR4 BitsFixed to 0. (R/O)See Appendix G.7, “VMX-Fixed Bits in CR4”(If CPUID.01H:ECX.[bit 9])489H1161IA32_VMX_CR4_FI UniqueXED1Capability Reporting Register of CR4 BitsFixed to 1. (R/O)See Appendix G.7, “VMX-Fixed Bits in CR4”(If CPUID.01H:ECX.[bit 9])48AH1162IA32_VMX_VMCS_ENUMUniqueCapability Reporting Register of VMCS FieldEnumeration. (R/O).See Appendix G.8, “VMCS Enumeration”(If CPUID.01H:ECX.[bit 9])Vol.
3 B-93MODEL-SPECIFIC REGISTERS (MSRS)Table B-5. MSRs in Intel Core Solo, Intel Core Duo Processors, and Dual-core IntelXeon Processor LV (Contd.)RegisterAddressHexDec48BH1163Register NameShared/UniqueIA32_VMX_PROCB UniqueASED_CTLS2Bit DescriptionCapability Reporting Register of SecondaryProcessor-based VM-execution Controls.(R/O)See Appendix G.2, “VM-Execution Controls”(If CPUID.01H:ECX.[bit 9] andIA32_VMX_PROCBASED_CTLS[bit 63])600H1536IA32_DS_AREAUniqueDS Save Area.
(R/W)Points to the DS buffer management area,which is used to manage the BTS and PEBSbuffers.See Section 18.15.4, “Debug Store (DS)Mechanism.”31:0DS Buffer Management Area.Linear address of the first byte of the DSbuffer management area.63:32C000_0080HB.4IA32_EFERReserved.Unique10:0Reserved.11Execute Disable Bit Enable.63:12ReservedMSRS IN THE PENTIUM M PROCESSORModel-specific registers (MSRs) for the Pentium M processor are similar to thosedescribed in Section B.5 for P6 family processors.
The following table describes newMSRs and MSRs whose behavior has changed on the Pentium M processor.B-94 Vol. 3MODEL-SPECIFIC REGISTERS (MSRS)Table B-6. MSRs in Pentium M ProcessorsRegisterAddressRegister NameBit DescriptionHexDec0H0P5_MC_ADDRSee Appendix B.6, “MSRs in Pentium Processors.”1H1P5_MC_TYPESee Appendix B.6, “MSRs in Pentium Processors.”10H16IA32_TIME_STAMP_COUNTERSee Section 18.10, “Time-Stamp Counter.”17H23IA32_PLATFORM_IDPlatform ID. (R)The operating system can use this MSR todetermine “slot” information for the processor andthe proper microcode update to load.49:0Reserved.52:50Platform Id.
(R)Contains information concerning the intendedplatform for the processor.52000011112AH4251001100115001010101Processor Flag 0Processor Flag 1Processor Flag 2Processor Flag 3Processor Flag 4Processor Flag 5Processor Flag 6Processor Flag 763:53Reserved.MSR_EBL_CR_POWERONProcessor Hard Power-On Configuration.(R/W) Enables and disables processor features. (R)Indicates current processor configuration.0Reserved.1Data Error Checking Enable.
(R/W)1 = Enabled0 = DisabledAlways 0 on the Pentium M processor.2Response Error Checking Enable. (R/W)FRCERR Observation Enable:1 = Enabled0 = DisabledAlways 0 on the Pentium M processor.Vol. 3 B-95MODEL-SPECIFIC REGISTERS (MSRS)Table B-6. MSRs in Pentium M Processors (Contd.)RegisterAddressHexRegister NameBit DescriptionDec3AERR# Drive Enable. (R/W)1 = Enabled0 = DisabledAlways 0 on the Pentium M processor.4BERR# Enable for initiator bus requests.
(R/W)1 = Enabled0 = DisabledAlways 0 on the Pentium M processor.5Reserved.6BERR# Driver Enable for initiator internalerrors. (R/W)1 = Enabled0 = DisabledAlways 0 on the Pentium M processor.7BINIT# Driver Enable. (R/W)1 = Enabled0 = DisabledAlways 0 on the Pentium M processor.8Output Tri-state Enabled. (R/O)1 = Enabled0 = Disabled9Execute BIST. (R/O)1 = Enabled0 = Disabled10AERR# Observation Enabled. (R/O)1 = Enabled0 = DisabledAlways 0 on the Pentium M processor.11Reserved.12BINIT# Observation Enabled. (R/O)1 = Enabled0 = DisabledAlways 0 on the Pentium M processor.B-96 Vol. 3MODEL-SPECIFIC REGISTERS (MSRS)Table B-6. MSRs in Pentium M Processors (Contd.)RegisterAddressHexRegister NameBit DescriptionDec13In Order Queue Depth. (R/O)1=10=8141 MByte Power on Reset Vector. (R/O)1 = 1 MByte0 = 4 GBytesAlways 0 on the Pentium M processor.15Reserved.17:16APIC Cluster ID.
(R/O)Always 00B on the Pentium M processor.18System Bus Frequency. (R/O)0 = 100 MHz1 = ReservedAlways 0 on the Pentium M processor.19Reserved.21: 20Symmetric Arbitration ID. (R/O)Always 00B on the Pentium M processor.40H6426:22Clock Frequency Ratio (R/O)MSR_LASTBRANCH_0Last Branch Record 0. (R/W)One of 8 last branch record registers on the lastbranch record stack: bits 31-0 hold the ‘from’address and bits 63-32 hold the to address.See also:• Last Branch Record Stack TOS at 1C9H• Section 18.8, “Last Branch, Interrupt, andException Recording (Pentium M Processors)”41H65MSR_LASTBRANCH_142H66MSR_LASTBRANCH_2Last Branch Record 1.
(R/W)See description of MSR_LASTBRANCH_0.Last Branch Record 2. (R/W)See description<b>Текст обрезан, так как является слишком большим</b>.
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