Volume 3B System Programming Guide_ Part 2 (794104), страница 98
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3MODEL-SPECIFIC REGISTERS (MSRS)Table B-2. MSRs in the Pentium 4 and Intel Xeon Processors (Contd.)RegisterAddressRegister NameFields and FlagsModelAvailabilityShared/Unique1Bit DescriptionHexDec36DH877MSR_IQ_CCCR10, 1, 2,3, 4, 6SharedSee Section 18.15.3, “CCCR MSRs.”36EH878MSR_IQ_CCCR20, 1, 2,3, 4, 6SharedSee Section 18.15.3, “CCCR MSRs.”36FH879MSR_IQ_CCCR30, 1, 2,3, 4, 6SharedSee Section 18.15.3, “CCCR MSRs.”370H880MSR_IQ_CCCR40, 1, 2,3, 4, 6SharedSee Section 18.15.3, “CCCR MSRs.”371H881MSR_IQ_CCCR50, 1, 2,3, 4, 6SharedSee Section 18.15.3, “CCCR MSRs.”3A0H928MSR_BSU_ESCR00, 1, 2,3, 4, 6SharedSee Section 18.15.1, “ESCR MSRs.”3A1H929MSR_BSU_ESCR10, 1, 2,3, 4, 6SharedSee Section 18.15.1, “ESCR MSRs.”3A2H930MSR_FSB_ESCR00, 1, 2,3, 4, 6SharedSee Section 18.15.1, “ESCR MSRs.”3A3H931MSR_FSB_ESCR10, 1, 2,3, 4, 6SharedSee Section 18.15.1, “ESCR MSRs.”3A4H932MSR_FIRM_ESCR00, 1, 2,3, 4, 6SharedSee Section 18.15.1, “ESCR MSRs.”3A5H933MSR_FIRM_ESCR10, 1, 2,3, 4, 6SharedSee Section 18.15.1, “ESCR MSRs.”3A6H934MSR_FLAME_ESCR00, 1, 2,3, 4, 6SharedSee Section 18.15.1, “ESCR MSRs.”3A7H935MSR_FLAME_ESCR10, 1, 2,3, 4, 6SharedSee Section 18.15.1, “ESCR MSRs.”3A8H936MSR_DAC_ESCR00, 1, 2,3, 4, 6SharedSee Section 18.15.1, “ESCR MSRs.”3A9H937MSR_DAC_ESCR10, 1, 2,3, 4, 6SharedSee Section 18.15.1, “ESCR MSRs.”3AAH938MSR_MOB_ESCR00, 1, 2,3, 4, 6SharedSee Section 18.15.1, “ESCR MSRs.”3ABH939MSR_MOB_ESCR10, 1, 2,3, 4, 6SharedSee Section 18.15.1, “ESCR MSRs.”Vol.
3 B-57MODEL-SPECIFIC REGISTERS (MSRS)Table B-2. MSRs in the Pentium 4 and Intel Xeon Processors (Contd.)RegisterAddressRegister NameFields and FlagsModelAvailabilityShared/Unique1Bit DescriptionHexDec3ACH940MSR_PMH_ESCR00, 1, 2,3, 4, 6SharedSee Section 18.15.1, “ESCR MSRs.”3ADH941MSR_PMH_ESCR10, 1, 2,3, 4, 6SharedSee Section 18.15.1, “ESCR MSRs.”3AEH942MSR_SAAT_ESCR00, 1, 2,3, 4, 6SharedSee Section 18.15.1, “ESCR MSRs.”3AFH943MSR_SAAT_ESCR10, 1, 2,3, 4, 6SharedSee Section 18.15.1, “ESCR MSRs.”3B0H944MSR_U2L_ESCR00, 1, 2,3, 4, 6SharedSee Section 18.15.1, “ESCR MSRs.”3B1H945MSR_U2L_ESCR10, 1, 2,3, 4, 6SharedSee Section 18.15.1, “ESCR MSRs.”3B2H946MSR_BPU_ESCR00, 1, 2,3, 4, 6SharedSee Section 18.15.1, “ESCR MSRs.”3B3H947MSR_BPU_ESCR10, 1, 2,3, 4, 6SharedSee Section 18.15.1, “ESCR MSRs.”3B4H948MSR_IS_ESCR00, 1, 2,3, 4, 6SharedSee Section 18.15.1, “ESCR MSRs.”3B5H949MSR_IS_ESCR10, 1, 2,3, 4, 6SharedSee Section 18.15.1, “ESCR MSRs.”3B6H950MSR_ITLB_ESCR00, 1, 2,3, 4, 6SharedSee Section 18.15.1, “ESCR MSRs.”3B7H951MSR_ITLB_ESCR10, 1, 2,3, 4, 6SharedSee Section 18.15.1, “ESCR MSRs.”3B8H952MSR_CRU_ESCR00, 1, 2,3, 4, 6SharedSee Section 18.15.1, “ESCR MSRs.”3B9H953MSR_CRU_ESCR10, 1, 2,3, 4, 6SharedSee Section 18.15.1, “ESCR MSRs.”3BAH954MSR_IQ_ESCR00, 1, 2SharedSee Section 18.15.1, “ESCR MSRs.”This MSR is not available on laterprocessors.
It is only available onprocessor family 0FH, models01H-02H.B-58 Vol. 3MODEL-SPECIFIC REGISTERS (MSRS)Table B-2. MSRs in the Pentium 4 and Intel Xeon Processors (Contd.)RegisterAddressHexDec3BBH955Register NameFields and FlagsMSR_IQ_ESCR1ModelAvailabilityShared/Unique10, 1, 2SharedBit DescriptionSee Section 18.15.1, “ESCR MSRs.”This MSR is not available on laterprocessors. It is only available onprocessor family 0FH, models01H-02H.3BCH956MSR_RAT_ESCR00, 1, 2,3, 4, 6SharedSee Section 18.15.1, “ESCR MSRs.”3BDH957MSR_RAT_ESCR10, 1, 2,3, 4, 6SharedSee Section 18.15.1, “ESCR MSRs.”3BEH958MSR_SSU_ESCR00, 1, 2,3, 4, 6SharedSee Section 18.15.1, “ESCR MSRs.”3C0H960MSR_MS_ESCR00, 1, 2,3, 4, 6SharedSee Section 18.15.1, “ESCR MSRs.”3C1H961MSR_MS_ESCR10, 1, 2,3, 4, 6SharedSee Section 18.15.1, “ESCR MSRs.”3C2H962MSR_TBPU_ESCR00, 1, 2,3, 4, 6SharedSee Section 18.15.1, “ESCR MSRs.”3C3H963MSR_TBPU_ESCR10, 1, 2,3, 4, 6SharedSee Section 18.15.1, “ESCR MSRs.”3C4H964MSR_TC_ESCR00, 1, 2,3, 4, 6SharedSee Section 18.15.1, “ESCR MSRs.”3C5H965MSR_TC_ESCR10, 1, 2,3, 4, 6SharedSee Section 18.15.1, “ESCR MSRs.”3C8H968MSR_IX_ESCR00, 1, 2,3, 4, 6SharedSee Section 18.15.1, “ESCR MSRs.”3C9H969MSR_IX_ESCR00, 1, 2,3, 4, 6SharedSee Section 18.15.1, “ESCR MSRs.”3CAH970MSR_ALF_ESCR00, 1, 2,3, 4, 6SharedSee Section 18.15.1, “ESCR MSRs.”3CBH971MSR_ALF_ESCR10, 1, 2,3, 4, 6SharedSee Section 18.15.1, “ESCR MSRs.”3CCH972MSR_CRU_ESCR20, 1, 2,3, 4, 6SharedSee Section 18.15.1, “ESCR MSRs.”3CDH973MSR_CRU_ESCR30, 1, 2,3, 4, 6SharedSee Section 18.15.1, “ESCR MSRs.”Vol.
3 B-59MODEL-SPECIFIC REGISTERS (MSRS)Table B-2. MSRs in the Pentium 4 and Intel Xeon Processors (Contd.)RegisterAddressRegister NameFields and FlagsModelAvailabilityShared/Unique1Bit DescriptionHexDec3E0H992MSR_CRU_ESCR40, 1, 2,3, 4, 6SharedSee Section 18.15.1, “ESCR MSRs.”3E1H993MSR_CRU_ESCR50, 1, 2,3, 4, 6SharedSee Section 18.15.1, “ESCR MSRs.”3FOH1008MSR_TC_PRECISE_EVENT0, 1, 2,3, 4, 6SharedSee Section 18.15.1, “ESCR MSRs.”3F1H1009MSR_PEBS_ENABLE0, 1, 2,3, 4, 6SharedPrecise Event-Based Sampling(PEBS).
(R/W)Controls the enabling of preciseevent sampling and replay tagging.12:0See Table A-10.23:13Reserved.24UOP Tag.Enables replay tagging when set.25ENABLE_PEBS_MY_THR. (R/W)Enables PEBS for the target logicalprocessor when set; disables PEBSwhen clear (default).See Section 18.16.3,“IA32_PEBS_ENABLE MSR,” for anexplanation of the target logicalprocessor.This bit is called ENABLE_PEBS inIA-32 processors that do notsupport Hyper-ThreadingTechnology.B-60 Vol. 3MODEL-SPECIFIC REGISTERS (MSRS)Table B-2. MSRs in the Pentium 4 and Intel Xeon Processors (Contd.)RegisterAddressHexRegister NameFields and FlagsDecModelAvailabilityShared/Unique126Bit DescriptionENABLE_PEBS_OTH_THR.
(R/W)Enables PEBS for the target logicalprocessor when set; disables PEBSwhen clear (default).See Section 18.16.3,“IA32_PEBS_ENABLE MSR,” for anexplanation of the target logicalprocessor.This bit is reserved for IA-32processors that do not supportHyper-Threading Technology.63:27Reserved.3F2H1010MSR_PEBS_MATRIX_VERT0, 1, 2,3, 4, 6SharedSee Table A-10.400H1024IA32_MC0_CTL0, 1, 2,3, 4, 6SharedSee Section 14.3.2.1,“IA32_MCi_CTL MSRs.”401H1025IA32_MC0_STATUS0, 1, 2,3, 4, 6SharedSee Section 14.3.2.2,“IA32_MCi_STATUS MSRS.”402H1026IA32_MC0_ADDR0, 1, 2,3, 4, 6SharedSee Section 14.3.2.3,“IA32_MCi_ADDR MSRs.”The IA32_MC0_ADDR register iseither not implemented orcontains no address if the ADDRVflag in the IA32_MC0_STATUSregister is clear.When not implemented in theprocessor, all reads and writes tothis MSR will cause a generalprotection exception.403H1027IA32_MC0_MISC0, 1, 2,3, 4, 6SharedSee Section 14.3.2.4,“IA32_MCi_MISC MSRs.”The IA32_MC0_MISC MSR is eithernot implemented or does notcontain additional information ifthe MISCV flag in theIA32_MC0_STATUS register isclear.Vol.
3 B-61MODEL-SPECIFIC REGISTERS (MSRS)Table B-2. MSRs in the Pentium 4 and Intel Xeon Processors (Contd.)RegisterAddressHexRegister NameFields and FlagsDecModelAvailabilityShared/Unique1Bit DescriptionWhen not implemented in theprocessor, all reads and writes tothis MSR will cause a generalprotection exception.404H1028IA32_MC1_CTL0, 1, 2,3, 4, 6SharedSee Section 14.3.2.1,“IA32_MCi_CTL MSRs.”405H1029IA32_MC1_STATUS0, 1, 2,3, 4, 6SharedSee Section 14.3.2.2,“IA32_MCi_STATUS MSRS.”406H1030IA32_MC1_ADDR0, 1, 2,3, 4, 6SharedSee Section 14.3.2.3,“IA32_MCi_ADDR MSRs.”The IA32_MC1_ADDR register iseither not implemented orcontains no address if the ADDRVflag in the IA32_MC1_STATUSregister is clear.When not implemented in theprocessor, all reads and writes tothis MSR will cause a generalprotection exception.407H1031IA32_MC1_MISCSharedSee Section 14.3.2.4,“IA32_MCi_MISC MSRs.”The IA32_MC1_MISC MSR is eithernot implemented or does notcontain additional information ifthe MISCV flag in theIA32_MC1_STATUS register isclear.When not implemented in theprocessor, all reads and writes tothis MSR will cause a generalprotection exception.408H1032IA32_MC2_CTL0, 1, 2,3, 4, 6SharedSee Section 14.3.2.1,“IA32_MCi_CTL MSRs.”409H1033IA32_MC2_STATUS0, 1, 2,3, 4, 6SharedSee Section 14.3.2.2,“IA32_MCi_STATUS MSRS.”B-62 Vol.
3MODEL-SPECIFIC REGISTERS (MSRS)Table B-2. MSRs in the Pentium 4 and Intel Xeon Processors (Contd.)RegisterAddressHexDec40AH1034Register NameFields and FlagsModelAvailabilityShared/Unique1IA32_MC2_ADDRBit DescriptionSee Section 14.3.2.3,“IA32_MCi_ADDR MSRs.”The IA32_MC2_ADDR register iseither not implemented orcontains no address if the ADDRVflag in the IA32_MC2_STATUSregister is clear.
When notimplemented in the processor, allreads and writes to this MSR willcause a general-protectionexception.40BH1035IA32_MC2_MISCSee Section 14.3.2.4,“IA32_MCi_MISC MSRs.”The IA32_MC2_MISC MSR is eithernot implemented or does notcontain additional information ifthe MISCV flag in theIA32_MC2_STATUS register isclear.When not implemented in theprocessor, all reads and writes tothis MSR will cause a generalprotection exception.40CH1036IA32_MC3_CTL0, 1, 2,3, 4, 6SharedSee Section 14.3.2.1,“IA32_MCi_CTL MSRs.”40DH1037IA32_MC3_STATUS0, 1, 2,3, 4, 6SharedSee Section 14.3.2.2,“IA32_MCi_STATUS MSRS.”40EH1038IA32_MC3_ADDR0, 1, 2,3, 4, 6SharedSee Section 14.3.2.3,“IA32_MCi_ADDR MSRs.”The IA32_MC3_ADDR register iseither not implemented orcontains no address if the ADDRVflag in the IA32_MC3_STATUSregister is clear.When not implemented in theprocessor, all reads and writes tothis MSR will cause a generalprotection exception.Vol.
3 B-63MODEL-SPECIFIC REGISTERS (MSRS)Table B-2. MSRs in the Pentium 4 and Intel Xeon Processors (Contd.)RegisterAddressHexDec40FH1039Register NameFields and FlagsIA32_MC3_MISCModelAvailabilityShared/Unique10, 1, 2,3, 4, 6SharedBit DescriptionSee Section 14.3.2.4,“IA32_MCi_MISC MSRs.”The IA32_MC3_MISC MSR is eithernot implemented or does notcontain additional information ifthe MISCV flag in theIA32_MC3_STATUS register isclear.When not implemented in theprocessor, all reads and writes tothis MSR will cause a generalprotection exception.410H1040IA32_MC4_CTL0, 1, 2,3, 4, 6SharedSee Section 14.3.2.1,“IA32_MCi_CTL MSRs.”411H1041IA32_MC4_STATUS0, 1, 2,3, 4, 6SharedSee Section 14.3.2.2,“IA32_MCi_STATUS MSRS.”412H1042IA32_MC4_ADDRSee Section 14.3.2.3,“IA32_MCi_ADDR MSRs.”The IA32_MC2_ADDR register iseither not implemented orcontains no address if the ADDRVflag in the IA32_MC4_STATUSregister is clear.When not implemented in theprocessor, all reads and writes tothis MSR will cause a generalprotection exception.413H1043IA32_MC4_MISCSee Section 14.3.2.4,“IA32_MCi_MISC MSRs.”The IA32_MC2_MISC MSR is eithernot implemented or does notcontain additional information ifthe MISCV flag in theIA32_MC4_STATUS register isclear.B-64 Vol.
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