Volume 3B System Programming Guide_ Part 2 (794104), страница 93

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(R)Contains an index (bits 0-3) that points to theMSR containing the most recent branch record.See MSR_LASTBRANCH_0 (at 40H).1D9H473IA32_DEBUGCTLUniqueDebug Control. (R/W)Controls how several debug features are used.Bit definitions are discussed in the referencedsection.1DDH1DEH477478MSR_LER_FROM_LIPUniqueMSR_LER_TO_LIPUniqueLast Exception Record From Linear IP. (R)Contains a pointer to the last branchinstruction that the processor executed priorto the last exception that was generated orthe last interrupt that was handled.Last Exception Record To Linear IP. (R)This area contains a pointer to the target ofthe last branch instruction that the processorexecuted prior to the last exception that wasgenerated or the last interrupt that washandled.200H512MTRRphysBase0Unique201H513MTRRphysMask0Unique202H514MTRRphysBase1Unique203H515MTRRphysMask1Unique204H516MTRRphysBase2Unique205H517MTRRphysMask2Unique206H518MTRRphysBase3Unique207H519MTRRphysMask3Unique208H520MTRRphysBase4Unique209H521MTRRphysMask4Unique20AH522MTRRphysBase5Unique20BH523MTRRphysMask5Unique20CH524MTRRphysBase6Unique20DH525MTRRphysMask6UniqueVol.

3 B-17MODEL-SPECIFIC REGISTERS (MSRS)Table B-1. MSRs in Processors Based on Intel Core Microarchitecture (Contd.)RegisterAddressRegister NameShared/UniqueHexDec20EH526MTRRphysBase7Unique20FH527MTRRphysMask7Unique250H592MTRRfix64K_00000Unique258H600MTRRfix16K_80000Unique259H601MTRRfix16K_A0000Unique268H616MTRRfix4K_C0000Unique269H617MTRRfix4K_C8000Unique26AH618MTRRfix4K_D0000Unique26BH619MTRRfix4K_D8000Unique26CH620MTRRfix4K_E0000Unique26DH621MTRRfix4K_E8000Unique26EH622MTRRfix4K_F0000Unique26FH623MTRRfix4K_F8000Unique2FFH767IA32_MTRR_DEF_TYPEUniqueBit DescriptionDefault Memory Types.

(R/W)Sets the memory type for the regions ofphysical memory that are not mapped by theMTRRs.See Section 10.11.2.1,“IA32_MTRR_DEF_TYPE MSR.”309H777IA32_FIXED_CTR0UniqueFixed-Function Performance CounterRegister 0. (R/W)When enabled, this performance countercounts instruction retired event.B-18 Vol.

3MODEL-SPECIFIC REGISTERS (MSRS)Table B-1. MSRs in Processors Based on Intel Core Microarchitecture (Contd.)RegisterAddressHexDec309H777Register NameMSR_PERF_FIXED_CTR0Shared/UniqueUniqueBit DescriptionFixed-Function Performance CounterRegister 0. (R/W)When enabled, this performance countercounts instruction retired event.30AH778IA32_FIXED_CTR1UniqueFixed-Function Performance CounterRegister 1. (R/W)When enabled, this performance countercounts unhalted core cycle event.30AH778MSR_PERF_FIXED_CTR1UniqueFixed-Function Performance CounterRegister 1. (R/W)When enabled, this performance countercounts unhalted core cycle event.30BH779IA32_FIXED_CTR2UniqueFixed-Function Performance CounterRegister 2. (R/W)When enabled, this performance countercounts unhalted reference cycle event.30BH779MSR_PERF_FIXED_CTR2UniqueFixed-Function Performance CounterRegister 2.

(R/W)When enabled, this performance countercounts unhalted reference cycle event.345H837IA32_PERF_CAPABILITIESUniqueSee Section 18.5.1, “IA32_DEBUGCTL MSR.”38DH909IA32_FIXED_CTR_CTRLUniqueFixed-Function-Counter Control Register.(R/W)This register contains bit fields that configurethe fixed-function performance counterregisters.38DH909MSR_PERF_FIXED_CTR_CTRLUniqueFixed-Function-Counter Control Register.(R/W)This register contains bit fields that configurethe fixed-function performance counterregisters.38EH910IA32_PERF_GLOBAL_STAUSUniqueSee Section 18.14.2, “Global Counter ControlFacilities.”38EH910MSR_PERF_GLOBAL_STAUSUniqueSee Section 18.14.2, “Global Counter ControlFacilities.”Vol. 3 B-19MODEL-SPECIFIC REGISTERS (MSRS)Table B-1.

MSRs in Processors Based on Intel Core Microarchitecture (Contd.)RegisterAddressRegister NameShared/UniqueBit DescriptionHexDec38FH911IA32_PERF_GLOBAL_CTRLUniqueSee Section 18.14.2, “Global Counter ControlFacilities.”38FH911MSR_PERF_GLOBAL_CTRLUniqueSee Section 18.14.2, “Global Counter ControlFacilities.”390H912IA32_PERF_GLOBAL_OVF_CTRLUniqueSee Section 18.14.2, “Global Counter ControlFacilities.”390H912MSR_PERF_GLOBAL_OVF_CTRLUniqueSee Section 18.14.2, “Global Counter ControlFacilities.”3F1H1009IA32_PEBS_ENABLEUniqueSee Section 18.14.4, “Precise Even BasedSampling (PEBS).”0Enable PEBS on IA32_PMC0. (R/W)400H1024IA32_MC0_CTLUniqueSee Section 14.3.2.1, “IA32_MCi_CTL MSRs.”401H1025IA32_MC0_STATUSUniqueSee Section 14.3.2.2, “IA32_MCi_STATUSMSRS.”402H1026IA32_MC0_ADDRUniqueSee Section 14.3.2.3, “IA32_MCi_ADDR MSRs.”The IA32_MC0_ADDR register is either notimplemented or contains no address if theADDRV flag in the IA32_MC0_STATUS registeris clear.When not implemented in the processor, allreads and writes to this MSR will cause ageneral-protection exception.404H1028IA32_MC1_CTLUniqueSee Section 14.3.2.1, “IA32_MCi_CTL MSRs.”405H1029IA32_MC1_STATUSUniqueSee Section 14.3.2.2, “IA32_MCi_STATUSMSRS.”406H1030IA32_MC1_ADDRUniqueSee Section 14.3.2.3, “IA32_MCi_ADDR MSRs.”The IA32_MC1_ADDR register is either notimplemented or contains no address if theADDRV flag in the IA32_MC1_STATUS registeris clear.When not implemented in the processor, allreads and writes to this MSR will cause ageneral-protection exception.B-20 Vol.

3MODEL-SPECIFIC REGISTERS (MSRS)Table B-1. MSRs in Processors Based on Intel Core Microarchitecture (Contd.)RegisterAddressRegister NameShared/UniqueBit DescriptionHexDec408H1032IA32_MC2_CTLUniqueSee Section 14.3.2.1, “IA32_MCi_CTL MSRs.”409H1033IA32_MC2_STATUSUniqueSee Section 14.3.2.2, “IA32_MCi_STATUSMSRS.”40AH1034IA32_MC2_ADDRUniqueSee Section 14.3.2.3, “IA32_MCi_ADDR MSRs.”The IA32_MC2_ADDR register is either notimplemented or contains no address if theADDRV flag in the IA32_MC2_STATUS registeris clear.When not implemented in the processor, allreads and writes to this MSR will cause ageneral-protection exception.40CH1036MSR_MC4_CTLUniqueSee Section 14.3.2.1, “IA32_MCi_CTL MSRs.”40DH1037MSR_MC4_STATUSUniqueSee Section 14.3.2.2, “IA32_MCi_STATUSMSRS.”40EH1038MSR_MC4_ADDRUniqueSee Section 14.3.2.3, “IA32_MCi_ADDR MSRs.”The MSR_MC4_ADDR register is either notimplemented or contains no address if theADDRV flag in the MSR_MC4_STATUS registeris clear.When not implemented in the processor, allreads and writes to this MSR will cause ageneral-protection exception.410H1040MSR_MC3_CTLSee Section 14.3.2.1, “IA32_MCi_CTL MSRs.”411H1041MSR_MC3_STATUSSee Section 14.3.2.2, “IA32_MCi_STATUSMSRS.”412H1042MSR_MC3_ADDRUniqueSee Section 14.3.2.3, “IA32_MCi_ADDR MSRs.”The MSR_MC3_ADDR register is either notimplemented or contains no address if theADDRV flag in the MSR_MC3_STATUS registeris clear.When not implemented in the processor, allreads and writes to this MSR will cause ageneral-protection exception.413H1043MSR_MC3_MISCUnique414H1044MSR_MC5_CTLUniqueVol.

3 B-21MODEL-SPECIFIC REGISTERS (MSRS)Table B-1. MSRs in Processors Based on Intel Core Microarchitecture (Contd.)RegisterAddressRegister NameShared/UniqueHexDec415H1045MSR_MC5_STATUSUnique416H1046MSR_MC5_ADDRUnique417H1047MSR_MC5_MISCUnique480H1152IA32_VMX_BASICUniqueBit DescriptionReporting Register of Basic VMXCapabilities. (R/O)See Appendix G.1, “Basic VMX Information”(If CPUID.01H:ECX.[bit 9])481H1153IA32_VMX_PINBASED_CTLSUniqueCapability Reporting Register of Pin-basedVM-execution Controls. (R/O)See Appendix G.2, “VM-Execution Controls”(If CPUID.01H:ECX.[bit 9])482H1154IA32_VMX_PROCB UniqueASED_CTLSCapability Reporting Register of PrimaryProcessor-based VM-execution Controls.(R/O)See Appendix G.2, “VM-Execution Controls”(If CPUID.01H:ECX.[bit 9])483H1155IA32_VMX_EXIT_CTLSUniqueCapability Reporting Register of VM-exitControls.

(R/O)See Appendix G.3, “VM-Exit Controls”(If CPUID.01H:ECX.[bit 9])484H1156IA32_VMX_ENTRY_CTLSUniqueCapability Reporting Register of VM-entryControls. (R/O)See Appendix G.4, “VM-Entry Controls”(If CPUID.01H:ECX.[bit 9])485H1157IA32_VMX_MISCUniqueReporting Register of Miscellaneous VMXCapabilities. (R/O)See Appendix G.5, “Miscellaneous Data”(If CPUID.01H:ECX.[bit 9])486H1158IA32_VMX_CR0_FIXED0UniqueCapability Reporting Register of CR0 BitsFixed to 0.

(R/O)See Appendix G.6, “VMX-Fixed Bits in CR0”(If CPUID.01H:ECX.[bit 9])B-22 Vol. 3MODEL-SPECIFIC REGISTERS (MSRS)Table B-1. MSRs in Processors Based on Intel Core Microarchitecture (Contd.)RegisterAddressHexDec487H1159Register NameIA32_VMX_CR0_FIXED1Shared/UniqueUniqueBit DescriptionCapability Reporting Register of CR0 BitsFixed to 1. (R/O)See Appendix G.6, “VMX-Fixed Bits in CR0”(If CPUID.01H:ECX.[bit 9])488H1160IA32_VMX_CR4_FI UniqueXED0Capability Reporting Register of CR4 BitsFixed to 0.

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