Volume 3B System Programming Guide_ Part 2 (794104), страница 89
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Theseevents may occur a maximum of twoper clock.06HDATA_CACHE_LINES_WRITTEN_BACKNumber of dirty lines(all) that are writtenback, regardless of thecauseReplacements and internal andexternal snoops can all causewriteback and are counted.07HEXTERNAL_SNOOPSNumber of acceptedexternal snoopswhether they hit in thecode cache or datacache or neitherAssertions of EADS# outside of thesampling interval are not counted,and no internal snoops are counted.08HEXTERNAL_DATA_CACHE_SNOOP_HITSNumber of externalsnoops to the datacacheSnoop hits to a valid line in either thedata cache, the data line fill buffer, orone of the write back buffers are allcounted as hits.09HMEMORY ACCESSESIN BOTH PIPESNumber of data memoryreads or writes that arepaired in both pipes ofthe pipelineThese accesses are not necessarilyrun in parallel due to cache misses,bank conflicts, etc.0AHBANK CONFLICTSNumber of actual bankconflictsVol.
3 A-125PERFORMANCE-MONITORING EVENTSTable A-15. Events That Can Be Counted with Pentium ProcessorPerformance-Monitoring Counters (Contd.)EventNum.Mnemonic EventNameDescriptionComments0BHMISALIGNED DATAMEMORY OR I/OREFERENCESNumber of memory orI/O reads or writes thatare misalignedA 2- or 4-byte access is misalignedwhen it crosses a 4-byte boundary;an 8-byte access is misaligned whenit crosses an 8-byte boundary. Tenbyte accesses are treated as twoseparate accesses of 8 and 2 byteseach.0CHCODE READNumber of instructionreads; whether the readis cacheable ornoncacheableIndividual 8-byte noncacheableinstruction reads are counted.0DHCODE TLB MISSNumber of instructionreads that miss the codeTLB whether the read iscacheable ornoncacheableIndividual 8-byte noncacheableinstruction reads are counted.0EHCODE CACHE MISSNumber of instructionreads that miss theinternal code cache;whether the read iscacheable ornoncacheableIndividual 8-byte noncacheableinstruction reads are counted.0FHANY SEGMENTREGISTER LOADEDNumber of writes intoany segment register inreal or protected modeincluding the LDTR,GDTR, IDTR, and TRSegment loads are caused by explicitsegment register load instructions,far control transfers, and taskswitches.
Far control transfers andtask switches causing a privilegelevel change will signal this eventtwice. Interrupts and exceptions mayinitiate a far control transfer.10HReserved11HReservedA-126 Vol. 3PERFORMANCE-MONITORING EVENTSTable A-15. Events That Can Be Counted with Pentium ProcessorPerformance-Monitoring Counters (Contd.)EventNum.12HMnemonic EventNameBranchesDescriptionCommentsNumber of taken andnot taken branches,including: conditionalbranches, jumps, calls,returns, softwareinterrupts, and interruptreturnsAlso counted as taken branches areserializing instructions, VERR andVERW instructions, some segmentdescriptor loads, hardware interrupts(including FLUSH#), andprogrammatic exceptions that invokea trap or fault handler. The pipe isnot necessarily flushed.The number of branches actuallyexecuted is measured, not thenumber of predicted branches.13HBTB_HITSNumber of BTB hits thatoccurHits are counted only for thoseinstructions that are actuallyexecuted.14HTAKEN_BRANCH_OR_BTB_HITNumber of takenbranches or BTB hitsthat occurThis event type is a logical OR oftaken branches and BTB hits.
Itrepresents an event that may causea hit in the BTB. Specifically, it iseither a candidate for a space in theBTB or it is already in the BTB.15HPIPELINE FLUSHESNumber of pipelineflushes that occurThe counter will not be incrementedfor serializing instructions (serializinginstructions cause the prefetchqueue to be flushed but will nottrigger the Pipeline Flushed eventcounter) and software interrupts(software interrupts do not flush thepipeline).Pipeline flushes arecaused by BTB misseson taken branches,mispredictions,exceptions, interrupts,and some segmentdescriptor loads.Vol. 3 A-127PERFORMANCE-MONITORING EVENTSTable A-15. Events That Can Be Counted with Pentium ProcessorPerformance-Monitoring Counters (Contd.)EventNum.16HMnemonic EventNameINSTRUCTIONS_EXECUTEDDescriptionCommentsNumber of instructionsexecuted (up to two perclock)Invocations of a fault handler areconsidered instructions.
All hardwareand software interrupts andexceptions will also cause the countto be incremented. Repeat prefixedstring instructions will onlyincrement this counter once despitethe fact that the repeat loopexecutes the same instructionmultiple times until the loop criteriais satisfied.This applies to all the Repeat stringinstruction prefixes (i.e., REP, REPE,REPZ, REPNE, and REPNZ). Thiscounter will also only increment onceper each HLT instruction executedregardless of how many cycles theprocessor remains in the HALT state.17HINSTRUCTIONS_EXECUTED_ V PIPENumber of instructionsexecuted in the V_pipeThe event indicates thenumber of instructionsthat were paired.18HBUS_CYCLE_DURATIONThis event is the same as the 16Hevent except it only counts thenumber of instructions actuallyexecuted in the V-pipe.Number of clocks while The count includes HLDA, AHOLD,a bus cycle is in progress and BOFF# clocks.This event measuresbus use.19HWRITE_BUFFER_FULL_STALL_DURATIONNumber of clocks whilethe pipeline is stalleddue to full write buffersFull write buffers stall data memoryread misses, data memory writemisses, and data memory write hitsto S-state lines.
Stalls on I/Oaccesses are not included.1AHWAITING_FOR_DATA_MEMORY_READ_STALL_DURATIONNumber of clocks whilethe pipeline is stalledwhile waiting for datamemory readsData TLB Miss processing is alsoincluded in the count. The pipelinestalls while a data memory read is inprogress including attempts to readthat are not bypassed while a line isbeing filled.A-128 Vol. 3PERFORMANCE-MONITORING EVENTSTable A-15. Events That Can Be Counted with Pentium ProcessorPerformance-Monitoring Counters (Contd.)EventNum.Mnemonic EventNameDescriptionComments1BHSTALL ON WRITETO AN E- OR MSTATE LINENumber of stalls onwrites to E- or M-statelines1CHLOCKED BUS CYCLENumber of locked buscycles that occur as theresult of the LOCK prefixor LOCK instruction,page-table updates, anddescriptor table updatesOnly the read portion of the lockedread-modify-write is counted.
Splitlocked cycles (SCYC active) count astwo separate accesses. Cyclesrestarted due to BOFF# are not recounted.1DHI/O READ OR WRITECYCLENumber of bus cyclesdirected to I/O spaceMisaligned I/O accesses will generatetwo bus cycles. Bus cycles restarteddue to BOFF# are not re-counted.1EHNONCACHEABLE_MEMORY_READSCycles restarted due to BOFF# areNumber ofnoncacheablenot re-counted.instruction or datamemory read bus cycles.The count includes readcycles caused by TLBmisses, but does notinclude read cycles toI/O space.1FHPIPELINE_AGI_STALLSNumber of addressgeneration interlock(AGI) stallsAn AGI occurring in boththe U- and V- pipelinesin the same clock signalsthis event twice.20HReserved21HReservedAn AGI occurs when the instructionin the execute stage of either of Uor V-pipelines is writing to either theindex or base address register of aninstruction in the D2 (addressgeneration) stage of either the U- orV- pipelines.Vol.
3 A-129PERFORMANCE-MONITORING EVENTSTable A-15. Events That Can Be Counted with Pentium ProcessorPerformance-Monitoring Counters (Contd.)EventNum.22HMnemonic EventNameFLOPSDescriptionNumber of floatingpoint operations thatoccurCommentsNumber of floating-point adds,subtracts, multiplies, divides,remainders, and square roots arecounted. The transcendentalinstructions consist of multiple addsand multiplies and will signal thisevent multiple times. Instructionsgenerating the divide-by-zero,negative square root, specialoperand, or stack exceptions will notbe counted.Instructions generating all otherfloating-point exceptions will becounted.
The integer multiplyinstructions and other instructionswhich use the x87 FPU will becounted.23HBREAKPOINTMATCH ON DR0REGISTERNumber of matches onregister DR0 breakpointThe counters is incrementedregardless if the breakpoints areenabled or not. However, ifbreakpoints are not enabled, codebreakpoint matches will not bechecked for instructions executed inthe V-pipe and will not cause thiscounter to be incremented. (They arechecked on instruction executed inthe U-pipe only when breakpointsare not enabled.)These events correspond to thesignals driven on the BP[3:0] pins.Refer to Chapter 18, “Debugging andPerformance Monitoring” for moreinformation.24HBREAKPOINTMATCH ON DR1REGISTERNumber of matches onregister DR1 breakpointSee comment for 23H event.25HBREAKPOINTMATCH ON DR2REGISTERNumber of matches onregister DR2 breakpointSee comment for 23H event.A-130 Vol. 3PERFORMANCE-MONITORING EVENTSTable A-15.
Events That Can Be Counted with Pentium ProcessorPerformance-Monitoring Counters (Contd.)EventNum.Mnemonic EventNameDescriptionComments26HBREAKPOINTMATCH ON DR3REGISTERNumber of matches onregister DR3 breakpointSee comment for 23H event.27HHARDWAREINTERRUPTSNumber of taken INTRand NMI interrupts28HDATA_READ_OR_WRITENumber of memory datareads and/or writes(internal data cache hitand miss combined)Split cycle reads and writes arecounted individually.
Data MemoryReads that are part of TLB missprocessing are not included. Theseevents may occur at a maximum oftwo per clock. I/O is not included.29HDATA_READ_MISSOR_WRITE MISSNumber of memory readand/or write accessesthat miss the internaldata cache, whether ornot the access iscacheable ornoncacheableAdditional reads to the same cacheline after the first BRDY# of theburst line fill is returned but beforethe final (fourth) BRDY# has beenreturned, will not cause the counterto be incremented additional times.Data accesses that are part of TLBmiss processing are not included.Accesses directed to I/O space arenot included.2AHBUS_OWNERSHIP_LATENCY(Counter 0)The time from LRM busownership request tobus ownership granted(that is, the time fromthe earlier of a PBREQ(0), PHITM# or HITM#assertion to a PBGNTassertion)The ratio of the 2AH events countedon counter 0 and counter 1 is theaverage stall time due to busownership conflict.2AHBUS OWNERSHIPTRANSFERS(Counter 1)The number of bussownership transfers(that is, the number ofPBREQ (0) assertionsThe ratio of the 2AH events countedon counter 0 and counter 1 is theaverage stall time due to busownership conflict.2BHMMX_INSTRUCTIONS_EXECUTED_U-PIPE (Counter 0)Number of MMXinstructions executed inthe U-pipeVol.
3 A-131PERFORMANCE-MONITORING EVENTSTable A-15. Events That Can Be Counted with Pentium ProcessorPerformance-Monitoring Counters (Contd.)EventNum.Mnemonic EventNameDescription2BHMMX_INSTRUCTIONS_EXECUTED_V-PIPE (Counter 1)Number of MMXinstructions executed inthe V-pipe2CHCACHE_MSTATE_LINE_SHARING(Counter 0)Number of times aprocessor identified ahit to a modified line dueto a memory access inthe other processor(PHITM (O))2CHCACHE_LINE_SHARING(Counter 1)Number of shared datalines in the L1 cache(PHIT (O))2DHEMMS_INSTRUCTIONS_EXECUTED (Counter0)Number of EMMSinstructions executed2DHTRANSITIONS_BETWEEN_MMX_AND_FP_INSTRUCTIONS(Counter 1)Number of transitionsbetween MMX andfloating-pointinstructions or viceversa2EHBUS_UTILIZATION_DUE_TO_PROCESSOR_ACTIVITY(Counter 0)Number of clocks thebus is busy due to theprocessor’s own activity(the bus activity that iscaused by theprocessor)2EHWRITES_TO_NONCACHEABLE_MEMORY(Counter 1)Number of writeaccesses tononcacheable memoryA-132 Vol.
3CommentsIf the average memory latencies ofthe system are known, this eventenables the user to count the WriteBacks on PHITM(O) penalty and theLatency on Hit Modified(I) penalty.This event counts the first floatingpoint instruction following an MMXinstruction or first MMX instructionfollowing a floating-point instruction.The count may be used to estimateAn even count indicates the penalty in transitions betweenthe processor is in MMX floating-point state and MMX state.state. an odd countindicates it is in FP state.The count includes write cyclescaused by TLB misses and I/O writecycles.Cycles restarted due to BOFF# arenot re-counted.PERFORMANCE-MONITORING EVENTSTable A-15. Events That Can Be Counted with Pentium ProcessorPerformance-Monitoring Counters (Contd.)EventNum.Mnemonic EventNameDescriptionComments2FHSATURATING_MMX_INSTRUCTIONS_EXECUTED (Counter0)Number of saturatingMMX instructionsexecuted,independently ofwhether they actuallysaturated.2FHSATURATIONS_PERFORMED(Counter 1)Number of MMXinstructions that usedsaturating arithmeticwhen at least one of itsresults actuallysaturatedIf an MMX instruction operating on 4doublewords saturated in three outof the four results, the counter willbe incremented by one only.30HNUMBER_OF_CYCLES_NOT_IN_HALT_STATE(Counter 0)Number of cycles theprocessor is not idle dueto HLT instructionThis event will enable the user tocalculate “net CPI”.
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