Volume 3B System Programming Guide_ Part 2 (794104), страница 84
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3Counter numbersper ESCRESCR0: 8, 9ESCR Event Select02HESCR1: 10, 11ESCR[31:25]PERFORMANCE-MONITORING EVENTSTable A-5. Performance Monitoring Events Supported by Intel NetBurstMicroarchitecture for Non-Retirement Counting (Contd.)Event NameEvent ParametersParameter ValueESCR Event MaskCCCR SelectDescriptionESCR[24:9]Bit 15: ALLCount all μops operating on 64bit SIMD integer operands inmemory or MMX registers.01HCCCR[15:13]Event SpecificNotesIf an instruction contains morethan one 64-bit MMX μops, each64-bit MMX μop that is specifiedby the event mask will becounted.128bit_MMX_uopThis event increments for eachinteger SIMD SSE2 instruction,which operate on 128-bit SIMDoperands.ESCR restrictionsMSR_FIRM_ESCR0MSR_FIRM_ESCR1Counter numbersper ESCRESCR0: 8, 9ESCR Event Select1AHESCR1: 10, 11ESCR Event MaskCCCR SelectESCR[31:25]ESCR[24:9]Bit 15: ALLCount all μops operating on 128bit SIMD integer operands inmemory or XMM registers.01HCCCR[15:13]Event SpecificNotesIf an instruction contains morethan one 128-bit MMX μops, each128-bit MMX μop that is specifiedby the event mask will becounted.x87_FP_uopThis event increments for eachx87 floating-point μop, specifiedthrough the event mask fordetection.ESCR restrictionsMSR_FIRM_ESCR0MSR_FIRM_ESCR1Vol.
3 A-79PERFORMANCE-MONITORING EVENTSTable A-5. Performance Monitoring Events Supported by Intel NetBurstMicroarchitecture for Non-Retirement Counting (Contd.)Event NameEvent ParametersParameter ValueCounter numbersper ESCRESCR0: 8, 9ESCR Event Select04HESCR1: 10, 11ESCR Event MaskCCCR SelectDescriptionESCR[31:25]ESCR[24:9]Bit 15: ALLCount all x87 FP μops.01HCCCR[15:13]Event SpecificNotes1: If an instruction contains morethan one x87 FP μops, eachx87 FP μop that is specified bythe event mask will be counted.2: This event does not count x87FP μop for load, store, movebetween registers.TC_miscThis event counts miscellaneousevents detected by the TC.
Thecounter will count twice for eachoccurrence.ESCR restrictionsMSR_TC_ESCR0MSR_TC_ESCR1Counter numbersper ESCRESCR0: 4, 5ESCR Event Select06HESCR[31:25]CCCR Select01HCCCR[15:13]ESCR1: 6, 7ESCR Event MaskESCR[24:9]Bit 4: FLUSHglobal_power_eventsNumber of flushesThis event accumulates the timeduring which a processor is notstopped.ESCR restrictionsMSR_FSB_ESCR0MSR_FSB_ESCR1A-80 Vol. 3Counter numbersper ESCRESCR0: 0, 1ESCR Event Select013HESCR1: 2, 3ESCR[31:25]PERFORMANCE-MONITORING EVENTSTable A-5. Performance Monitoring Events Supported by Intel NetBurstMicroarchitecture for Non-Retirement Counting (Contd.)Event NameEvent ParametersParameter ValueESCR Event MaskBit 0: RunningDescriptionESCR[24:9]The processor is active (includesthe handling of HLT STPCLK andthrottling.CCCR Select06Htc_ms_xferCCCR[15:13]This event counts the number oftimes that uop delivery changedfrom TC to MS ROM.ESCR restrictionsMSR_MS_ESCR0MSR_MS_ESCR1Counter numbersper ESCRESCR0: 4, 5ESCR Event Select05HESCR1: 6, 7ESCR Event MaskCCCR SelectESCR[31:25]ESCR[24:9]Bit 0: CISCA TC to MS transfer occurred.0HCCCR[15:13]uop_queue_writesThis event counts the number ofvalid uops written to the uopqueue.
Specify one or more maskbits to select the source type ofwrites.ESCR restrictionsMSR_MS_ESCR0MSR_MS_ESCR1Counter numbersper ESCRESCR0: 4, 5ESCR Event Select09HESCR1: 6, 7ESCR Event MaskESCR[31:25]ESCR[24:9]Bit0: FROM_TC_BUILDThe uops being written are fromTC build mode.1: FROM_TC_DELIVERThe uops being written are fromTC deliver mode.2: FROM_ROMThe uops being written are frommicrocode ROM.Vol. 3 A-81PERFORMANCE-MONITORING EVENTSTable A-5. Performance Monitoring Events Supported by Intel NetBurstMicroarchitecture for Non-Retirement Counting (Contd.)Event NameEvent ParametersParameter ValueDescriptionCCCR Select0HCCCR[15:13]retired_mispredThis event counts retiringmispredicted branches by type._branch_typeESCR restrictionsMSR_TBPU_ESCR0MSR_TBPU_ESCR1Counter numbersper ESCRESCR0: 4, 5ESCR Event Select05HESCR1: 6, 7ESCR[30:25]ESCR[24:9]ESCR Event MaskBitCCCR Select1: CONDITIONALConditional jumps.2: CALLIndirect call branches.3: RETURNReturn branches.4: INDIRECTReturns, indirect calls, or indirectjumps.02HCCCR[15:13]Event SpecificNotesThis event may overcountconditional branches if:• Mispredictions cause the tracecache and delivery engine tobuild new traces.• When the processor's pipelineis being cleared.retired_branchThis event counts retiringbranches by type.
Specify one ormore mask bits to qualify thebranch by its type_typeESCR restrictionsMSR_TBPU_ESCR0MSR_TBPU_ESCR1A-82 Vol. 3Counter numbersper ESCRESCR0: 4, 5ESCR Event Select04HESCR1: 6, 7ESCR[30:25]PERFORMANCE-MONITORING EVENTSTable A-5. Performance Monitoring Events Supported by Intel NetBurstMicroarchitecture for Non-Retirement Counting (Contd.)Event NameEvent ParametersParameter ValueDescriptionESCR[24:9]ESCR Event MaskBitCCCR Select1: CONDITIONALConditional jumps.2: CALLDirect or indirect calls.3: RETURNReturn branches.4: INDIRECTReturns, indirect calls, or indirectjumps.02HCCCR[15:13]Event SpecificNotesThis event may overcountconditional branches if :• Mispredictions cause the tracecache and delivery engine tobuild new traces.• When the processor's pipelineis being cleared.resource_stallThis event monitors theoccurrence or latency of stalls inthe Allocator.ESCR restrictionsMSR_ALF_ESCR0MSR_ALF_ESCR1Counter numbersper ESCRESCR0: 12, 13, 16ESCR1: 14, 15, 17ESCR Event Select01HEvent MasksESCR[30:25]ESCR[24:9]BitCCCR SelectEvent SpecificNotesWC_Buffer5: SBFULLA Stall due to lack of store buffers.01HCCCR[15:13]This event may not be supportedin all models of the processorfamily.This event counts WriteCombining Buffer operations thatare selected by the event mask.Vol.
3 A-83PERFORMANCE-MONITORING EVENTSTable A-5. Performance Monitoring Events Supported by Intel NetBurstMicroarchitecture for Non-Retirement Counting (Contd.)Event NameEvent ParametersParameter ValueESCR restrictionsMSR_DAC_ESCR0DescriptionMSR_DAC_ESCR1Counter numbersper ESCRESCR0: 8, 9ESCR Event Select05HESCR1: 10, 11Event MasksESCR[30:25]ESCR[24:9]BitCCCR Select0: WCB_EVICTSWC Buffer evictions of all causes.1: WCB_FULL_EVICTWC Buffer eviction: no WC bufferis available.05HCCCR[15:13]Event SpecificNotesThis event is useful for detectingthe subset of 64K aliasing casesthat are more costly (i.e. 64Kaliasing cases involving stores) aslong as there are no significantcontributions due to writecombining buffer full or hitmodified conditions.b2b_cyclesThis event can be configured tocount the number back-to-backbus cycles using sub-event maskbits 1 through 6.ESCR restrictionsMSR_FSB_ESCR0MSR_FSB_ESCR1Counter numbersper ESCRESCR0: 0, 1ESCR Event Select016HESCR[30:25]Event MasksBitESCR[24:9]CCCR Select03HCCCR[15:13]Event SpecificNotesA-84 Vol.
3ESCR1: 2, 3This event may not be supportedin all models of the processorfamily.PERFORMANCE-MONITORING EVENTSTable A-5. Performance Monitoring Events Supported by Intel NetBurstMicroarchitecture for Non-Retirement Counting (Contd.)Event NameEvent ParametersParameter ValuebnrDescriptionThis event can be configured tocount bus not ready conditionsusing sub-event mask bits 0through 2.ESCR restrictionsMSR_FSB_ESCR0MSR_FSB_ESCR1Counter numbersper ESCRESCR0: 0, 1ESCR Event Select08HESCR[30:25]Event MasksBitESCR[24:9]CCCR Select03HCCCR[15:13]ESCR1: 2, 3Event SpecificNotesThis event may not be supportedin all models of the processorfamily.snoopThis event can be configured tocount snoop hit modified bustraffic using sub-event mask bits2, 6 and 7.ESCR restrictionsMSR_FSB_ESCR0MSR_FSB_ESCR1Counter numbersper ESCRESCR0: 0, 1ESCR Event Select06HESCR[30:25]Event MasksBitESCR[24:9]CCCR Select03HCCCR[15:13]ESCR1: 2, 3Event SpecificNotesThis event may not be supportedin all models of the processorfamily.ResponseThis event can be configured tocount different types ofresponses using sub-event maskbits 1,2, 8, and 9.ESCR restrictionsMSR_FSB_ESCR0MSR_FSB_ESCR1Vol.
3 A-85PERFORMANCE-MONITORING EVENTSTable A-5. Performance Monitoring Events Supported by Intel NetBurstMicroarchitecture for Non-Retirement Counting (Contd.)Event NameEvent ParametersParameter ValueDescriptionCounter numbersper ESCRESCR0: 0, 1ESCR Event Select04HESCR[30:25]Event MasksBitESCR[24:9]CCCR Select03HCCCR[15:13]ESCR1: 2, 3Event SpecificNotesThis event may not be supportedin all models of the processorfamily.Table A-6. Performance Monitoring Events For Intel NetBurstMicroarchitecture for At-Retirement CountingEvent NameEvent ParametersParameter Valuefront_end_eventDescriptionThis event counts the retirementof tagged μops, which arespecified through the front-endtagging mechanism. The eventmask specifies bogus or non-bogusμops.ESCR restrictionsMSR_CRU_ESCR2MSR_CRU_ESCR3Counter numbersper ESCRESCR2: 12, 13, 16ESCR Event Select08HESCR3: 14, 15, 17ESCR[31:25]ESCR[24:9]ESCR Event MaskBitA-86 Vol.
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