Volume 3B System Programming Guide_ Part 2 (794104), страница 81
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Table A-5 lists thenon-retirement events, and Table A-6 lists the at-retirement events. Tables A-8, A-9,and A-10 describes three sets of parameters that are available for three of theat-retirement counting events defined in Table A-6. Table A-11 shows which of thenon-retirement and at retirement events are logical processor specific (TS) (seeSection 18.16.4, “Performance Monitoring Events”) and which are non-logicalprocessor specific (TI).Some of the Pentium 4 and Intel Xeon processor performance-monitoring eventsmay be available only to specific models.
The performance-monitoring events listedin Tables A-5 and A-6 apply to processors with CPUID signature that matches familyA-54 Vol. 3PERFORMANCE-MONITORING EVENTSencoding 15, model encoding 0, 1, 2 3, 4, or 6. Table applies to processors with aCPUID signature that matches family encoding 15, model encoding 3, 4 or 6.The functionality of performance-monitoring events in Pentium 4 and Intel Xeonprocessors is also available when IA-32e mode is enabled.Table A-5. Performance Monitoring Events Supported by Intel NetBurstMicroarchitecture for Non-Retirement CountingEvent NameEvent ParametersParameter ValueTC_deliver_modeDescriptionThis event counts the duration (inclock cycles) of the operatingmodes of the trace cache anddecode engine in the processorpackage. The mode is specified byone or more of the event maskbits.ESCR restrictionsMSR_TC_ESCR0MSR_TC_ESCR1Counter numbersper ESCRESCR0: 4, 5ESCR Event Select01HESCR1: 6, 7ESCR[31:25]ESCR[24:9]ESCR Event MaskBit0: DDBoth logical processors are indeliver mode.1: DBLogical processor 0 is in delivermode and logical processor 1 is inbuild mode.2: DILogical processor 0 is in delivermode and logical processor 1 iseither halted, under a machineclear condition or transitioning toa long microcode flow.3: BDLogical processor 0 is in buildmode and logical processor 1 is indeliver mode.4: BBBoth logical processors are in buildmode.Vol.
3 A-55PERFORMANCE-MONITORING EVENTSTable A-5. Performance Monitoring Events Supported by Intel NetBurstMicroarchitecture for Non-Retirement Counting (Contd.)Event NameEvent ParametersCCCR SelectParameter ValueDescription5: BILogical processor 0 is in buildmode and logical processor 1 iseither halted, under a machineclear condition or transitioning toa long microcode flow.6: IDLogical processor 0 is eitherhalted, under a machine clearcondition or transitioning to a longmicrocode flow.
Logical processor1 is in deliver mode.7: IBLogical processor 0 is eitherhalted, under a machine clearcondition or transitioning to a longmicrocode flow. Logical processor1 is in build mode.01HCCCR[15:13]Event SpecificNotesIf only one logical processor isavailable from a physicalprocessor package, the eventmask should be interpreted aslogical processor 1 is halted. Eventmask bit 2 was previously knownas “DELIVER”, bit 5 was previouslyknown as “BUILD”.BPU_fetch_requestThis event counts instructionfetch requests of specifiedrequest type by the BranchPrediction unit. Specify one ormore mask bits to qualify therequest type(s).ESCR restrictionsMSR_BPU_ESCR0MSR_BPU_ESCR1Counter numbersper ESCRESCR0: 0, 1ESCR Event Select03HESCR1: 2, 3ESCR Event MaskESCR[24:9]Bit 0: TCMISSA-56 Vol.
3ESCR[31:25]Trace cache lookup missPERFORMANCE-MONITORING EVENTSTable A-5. Performance Monitoring Events Supported by Intel NetBurstMicroarchitecture for Non-Retirement Counting (Contd.)Event NameEvent ParametersParameter ValueDescriptionCCCR Select00HCCCR[15:13]ITLB_referenceThis event counts translationsusing the Instruction TranslationLook-aside Buffer (ITLB).ESCR restrictionsMSR_ITLB_ESCR0MSR_ITLB_ESCR1Counter numbersper ESCRESCR0: 0, 1ESCR Event Select18HESCR1: 2, 3ESCR[31:25]ESCR[24:9]ESCR Event MaskBitCCCR Select0: HITITLB hit1: MISSITLB miss2: HIT_UCUncacheable ITLB hit03HCCCR[15:13]Event SpecificNotesAll page references regardless ofthe page size are looked up asactual 4-KByte pages.
Use thepage_walk_type event with theITMISS mask for a moreconservative count.memory_cancelThis event counts the canceling ofvarious type of request in theData cache Address Control unit(DAC). Specify one or more maskbits to select the type of requeststhat are canceled.ESCR restrictionsMSR_DAC_ESCR0MSR_DAC_ESCR1Counter numbersper ESCRESCR0: 8, 9ESCR Event Select02HESCR1: 10, 11ESCR[31:25]Vol. 3 A-57PERFORMANCE-MONITORING EVENTSTable A-5.
Performance Monitoring Events Supported by Intel NetBurstMicroarchitecture for Non-Retirement Counting (Contd.)Event NameEvent ParametersParameter ValueDescriptionESCR[24:9]ESCR Event MaskBitCCCR Select2: ST_RB_FULLReplayed because no storerequest buffer is available3: 64K_CONFConflicts due to 64-KByte aliasing05HCCCR[15:13]Event SpecificNotesAll_CACHE_MISS includesuncacheable memory in countmemory_completeThis event counts the completionof a load split, store split,uncacheable (UC) split, or UC load.Specify one or more mask bits toselect the operations to becounted.ESCR restrictionsMSR_SAAT_ESCR0MSR_SAAT_ESCR1Counter numbersper ESCRESCR0: 8, 9ESCR Event Select08HESCR1: 10, 11ESCR Event MaskESCR[31:25]ESCR[24:9]BitCCCR Select0: LSCLoad split completed, excludingUC/WC loads1: SSCAny split stores completed02HCCCR[15:13]load_port_replayThis event counts replayed eventsat the load port.
Specify one ormore mask bits to select thecause of the replay.ESCR restrictionsMSR_SAAT_ESCR0MSR_SAAT_ESCR1A-58 Vol. 3Counter numbersper ESCRESCR0: 8, 9ESCR Event Select04HESCR1: 10, 11ESCR[31:25]PERFORMANCE-MONITORING EVENTSTable A-5. Performance Monitoring Events Supported by Intel NetBurstMicroarchitecture for Non-Retirement Counting (Contd.)Event NameEvent ParametersParameter ValueESCR Event MaskCCCR SelectDescriptionESCR[24:9]Bit 1: SPLIT_LDSplit load.02HCCCR[15:13]Event SpecificNotesMust use ESCR1 for at-retirementcountingstore_port_replayThis event counts replayed eventsat the store port.
Specify one ormore mask bits to select thecause of the replay.ESCR restrictionsMSR_SAAT_ESCR0MSR_SAAT_ESCR1Counter numbersper ESCRESCR0: 8, 9ESCR Event Select05HESCR1: 10, 11ESCR Event MaskCCCR SelectESCR[31:25]ESCR[24:9]Bit 1: SPLIT_STSplit store02HCCCR[15:13]Event SpecificNotesMust use ESCR1 for at-retirementcountingMOB_load_replayThis event triggers if the memoryorder buffer (MOB) caused a loadoperation to be replayed. Specifyone or more mask bits to selectthe cause of the replay.ESCR restrictionsMSR_MOB_ESCR0MSR_MOB_ESCR1Counter numbersper ESCRESCR0: 0, 1ESCR Event Select03HESCR1: 2, 3ESCR[31:25]Vol.
3 A-59PERFORMANCE-MONITORING EVENTSTable A-5. Performance Monitoring Events Supported by Intel NetBurstMicroarchitecture for Non-Retirement Counting (Contd.)Event NameEvent ParametersParameter ValueESCR Event MaskDescriptionESCR[24:9]BitCCCR Select1: NO_STAReplayed because of unknownstore address3: NO_STDReplayed because of unknownstore data4: PARTIAL_DATAReplayed because of partiallyoverlapped data access betweenthe load and store operations5: UNALGN_ADDRReplayed because the lower 4 bitsof the linear address do not matchbetween the load and storeoperations02HCCCR[15:13]page_walk_typeThis event counts various typesof page walks that the page misshandler (PMH) performs.ESCR restrictionsMSR_PMH_ESCR0MSR_PMH_ESCR1Counter numbersper ESCRESCR0: 0, 1ESCR Event Select01HESCR1: 2, 3ESCR[31:25]ESCR[24:9]ESCR Event MaskBitCCCR SelectA-60 Vol.
30: DTMISSPage walk for a data TLB miss(either load or store)1: ITMISSPage walk for an instruction TLBmiss04HCCCR[15:13]PERFORMANCE-MONITORING EVENTSTable A-5. Performance Monitoring Events Supported by Intel NetBurstMicroarchitecture for Non-Retirement Counting (Contd.)Event NameEvent ParametersParameter ValueBSQ_cache_referenceDescriptionThis event counts cachereferences (2nd level cache or 3rdlevel cache) as seen by the busunit.Specify one or more mask bit toselect an access according to theaccess type (read type includesboth load and RFO, write typeincludes writebacks and evictions)and the access result (hit, misses).ESCR restrictionsMSR_BSU_ESCR0MSR_BSU_ESCR1Counter numbersper ESCRESCR0: 0, 1ESCR Event Select0CHESCR1: 2, 3ESCR[31:25]ESCR[24:9]Bit0: RD_2ndL_HITSRead 2nd level cache hit Shared(includes load and RFO)1: RD_2ndL_HITERead 2nd level cache hit Exclusive(includes load and RFO)2: RD_2ndL_HITMRead 2nd level cache hit Modified(includes load and RFO)3: RD_3rdL_HITSRead 3rd level cache hit Shared(includes load and RFO)4: RD_3rdL_HITERead 3rd level cache hit Exclusive(includes load and RFO)5: RD_3rdL_HITMRead 3rd level cache hit Modified(includes load and RFO)Vol.
3 A-61PERFORMANCE-MONITORING EVENTSTable A-5. Performance Monitoring Events Supported by Intel NetBurstMicroarchitecture for Non-Retirement Counting (Contd.)Event NameEvent ParametersParameter ValueDescriptionESCR Event Mask8: RD_2ndL_MISSRead 2nd level cache miss(includes load and RFO)9: RD_3rdL_MISSRead 3rd level cache miss(includes load and RFO)10: WR_2ndL_MISSA Writeback lookup from DACmisses the 2nd level cache(unlikely to happen)07HCCCR[15:13]CCCR SelectEvent SpecificNotes1: The implementation of thisevent in current Pentium 4 andXeon processors treats eithera load operation or a requestfor ownership (RFO) request asa “read” type operation.2: Currently this event causesboth over and undercountingby as much as a factor of twodue to an erratum.3: It is possible for a transactionthat is started as a prefetch tochange the transaction'sinternal status, making it nolonger a prefetch.
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