Volume 3B System Programming Guide_ Part 2 (794104), страница 78
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3This event counts the number of hardwareinterrupts received by the processor.PERFORMANCE-MONITORING EVENTSTable A-3. Non-Architectural Performance Eventsin Processors Based on Intel Core Microarchitecture (Contd.)EventNumUmaskValueCAH01HEvent NameDefinitionSIMD_COMP_INST_RETIRED.PACKED_SINGLERetiredcomputationalSSE packedsingleinstructionsDescription andCommentThis event counts the number ofcomputational SSE packed-singleinstructions retired.
Computationalinstructions perform arithmeticcomputations (for example: add, multiplyand divide).Instructions that perform load and storeoperations or logical operations, like XOR,OR, and AND are not counted by thisevent.CAH02HSIMD_COMP_INST_RETIRED.SCALAR_SINGLERetiredcomputationalSSE scalarsingleinstructionsThis event counts the number ofcomputational SSE scalar-singleinstructions retired. Computationalinstructions perform arithmeticcomputations (for example: add, multiplyand divide).Instructions that perform load and storeoperations or logical operations, like XOR,OR, and AND are not counted by thisevent.CAH04HSIMD_COMP_INST_RETIRED.PACKED_DOUBLERetiredcomputationalSSE2 packeddoubleinstructionsThis event counts the number ofcomputational SSE2 packed-doubleinstructions retired. Computationalinstructions perform arithmeticcomputations (for example: add, multiplyand divide).Instructions that perform load and storeoperations or logical operations, like XOR,OR, and AND are not counted by thisevent.CAH08HSIMD_COMP_INST_ RetiredRETIRED.SCALAR_ computationalDOUBLESSE2 scalardoubleinstructionsThis event counts the number ofcomputational SSE2 scalar-doubleinstructions retired.
Computationalinstructions perform arithmeticcomputations (for example: add, multiplyand divide).Instructions that perform load and storeoperations or logical operations, like XOR,OR, and AND are not counted by thisevent.Vol. 3 A-37PERFORMANCE-MONITORING EVENTSTable A-3. Non-Architectural Performance Eventsin Processors Based on Intel Core Microarchitecture (Contd.)EventNumUmaskValueCBH01HEvent NameDefinitionMEM_LOAD_RETIRED.L1D_MISSRetired loadsthat miss theL1 data cache(precise event)Description andCommentThis event counts the number of retiredload operations that missed the L1 datacache. This includes loads from cache linesthat are currently being fetched, due to aprevious L1 data cache miss to the samecache line.This event counts loads from cacheablememory only.
The event does not countloads by software prefetches.When this event is captured with theprecise event mechanism, the collectedsamples contain the address of theinstruction that was executed immediatelyafter the instruction that caused theevent.CBH02HMEM_LOAD_RETIRED.L1D_LINE_MISSL1 data cacheline missed byretired loads(precise event)This event counts the number of loadoperations that miss the L1 data cacheand send a request to the L2 cache tofetch the missing cache line.
That is themissing cache line fetching has not yetstarted.The event count is equal to the number ofcache lines fetched from the L2 cache byretired loads.This event counts loads from cacheablememory only. The event does not countloads by software prefetches.The event might not be counted if the loadis blocked (see LOAD_BLOCK events).When this event is captured with theprecise event mechanism, the collectedsamples contain the address of theinstruction that was executed immediatelyafter the instruction that caused theevent.A-38 Vol. 3PERFORMANCE-MONITORING EVENTSTable A-3. Non-Architectural Performance Eventsin Processors Based on Intel Core Microarchitecture (Contd.)EventNumUmaskValueCBH04HEvent NameDefinitionMEM_LOAD_RETIRED.L2_MISSRetired loadsthat miss theL2 cache(precise event)Description andCommentThis event counts the number of retiredload operations that missed the L2 cache.This event counts loads from cacheablememory only.
It does not count loads bysoftware prefetches.When this event is captured with theprecise event mechanism, the collectedsamples contain the address of theinstruction that was executed immediatelyafter the instruction that caused theevent.CBH08HMEM_LOAD_L2 cache lineRETIRED.L2_LINE_ missed byMISSretired loads(precise event)This event counts the number of loadoperations that miss the L2 cache andresult in a bus request to fetch the missingcache line. That is the missing cache linefetching has not yet started.This event count is equal to the number ofcache lines fetched from memory byretired loads.This event counts loads from cacheablememory only. The event does not countloads by software prefetches.The event might not be counted if the loadis blocked (see LOAD_BLOCK events).When this event is captured with theprecise event mechanism, the collectedsamples contain the address of theinstruction that was executed immediatelyafter the instruction that caused theevent.Vol.
3 A-39PERFORMANCE-MONITORING EVENTSTable A-3. Non-Architectural Performance Eventsin Processors Based on Intel Core Microarchitecture (Contd.)EventNumUmaskValueCBH10HEvent NameDefinitionDescription andCommentMEM_LOAD_RETIRED.DTLB_MISSRetired loadsthat miss theDTLB (preciseevent)This event counts the number of retiredloads that missed the DTLB.
The DTLBmiss is not counted if the load operationcauses a fault.This event counts loads from cacheablememory only. The event does not countloads by software prefetches.When this event is captured with theprecise event mechanism, the collectedsamples contain the address of theinstruction that was executed immediatelyafter the instruction that caused theevent.CCH01HFP_MMX_TRANS_TO_MMXTransitionsfrom FloatingPoint to MMXInstructionsThis event counts the first MMXinstructions following a floating-pointinstruction.
Use this event to estimate thepenalties for the transitions betweenfloating-point and MMX states.CCH02HFP_MMX_TRANS_TO_FPTransitionsfrom MMXInstructions toFloating PointInstructionsThis event counts the first floating-pointinstructions following any MMXinstruction. Use this event to estimate thepenalties for the transitions betweenfloating-point and MMX states.CDH00HSIMD_ASSISTSIMD assistsinvokedThis event counts the number of SIMDassists invoked.
SIMD assists are invokedwhen an EMMS instruction is executed,changing the MMX state in the floatingpoint stack.CEH00HSIMD_INSTR_RETIREDSIMDInstructionsretiredThis event counts the number of SIMDinstructions that retired.CFH00HSIMD_SAT_INSTR_ SaturatedRETIREDarithmeticinstructionsretiredA-40 Vol. 3This event counts the number of saturatedarithmetic SIMD instructions that retired.PERFORMANCE-MONITORING EVENTSTable A-3. Non-Architectural Performance Eventsin Processors Based on Intel Core Microarchitecture (Contd.)EventNumUmaskValueD2H01HEvent NameDefinitionRAT_STALLS.ROB_READ_PORTROB read portstalls cyclesDescription andCommentThis event counts the number of cycleswhen ROB read port stalls occurred, whichdid not allow new micro-ops to enter theout-of-order pipeline.Note that, at this stage in the pipeline,additional stalls may occur at the samecycle and prevent the stalled micro-opsfrom entering the pipe.
In such a case,micro-ops retry entering the executionpipe in the next cycle and the ROB-readport stall is counted again.D2H02HRAT_STALLS.PARTIAL_CYCLESPartial registerstall cyclesThis event counts the number of cyclesinstruction execution latency becamelonger than the defined latency becausethe instruction uses a register that waspartially written by previous instructions.D2H04HRAT_STALLS.FLAGSFlag stall cycles This event counts the number of cyclesduring which execution stalled due toseveral reasons, one of which is a partialflag register stall.A partial register stall may occur whentwo conditions are met:• an instruction modifies some, but notall, of the flags in the flag register• the next instruction, which depends onflags, depends on flags that were notmodified by this instructionD2H08HRAT_STALLS.FPSWFPU statusword stallThis event indicates that the FPU statusword (FPSW) is written.
To obtain thenumber of times the FPSW is writtendivide the event count by 2.The FPSW is written by instructions withlong latency; a small count may indicate ahigh penalty.D2H0FHRAT_STALLS.ANYAll RAT stallcyclesThis event counts the number of stallcycles due to conditions described by:••••RAT_STALLS.ROB_READ_PORTRAT_STALLS.PARTIALRAT_STALLS.FLAGSRAT_STALLS.FPSW.Vol. 3 A-41PERFORMANCE-MONITORING EVENTSTable A-3. Non-Architectural Performance Eventsin Processors Based on Intel Core Microarchitecture (Contd.)EventNumUmaskValueD4HDescription andCommentEvent NameDefinition01HSEG_RENAME_STALLS.ESSegmentrename stalls ESThis event counts the number of stalls dueto the lack of renaming resources for theES segment register.
If a segment isrenamed, but not retired and a secondupdate to the same segment occurs, a stalloccurs in the front-end of the pipeline untilthe renamed segment retires.D4H02HSEG_RENAME_STALLS.DSSegmentrename stalls DSThis event counts the number of stalls dueto the lack of renaming resources for theDS segment register. If a segment isrenamed, but not retired and a secondupdate to the same segment occurs, a stalloccurs in the front-end of the pipeline untilthe renamed segment retires.D4H04HSEG_RENAME_STALLS.FSSegmentrename stalls FSThis event counts the number of stalls dueto the lack of renaming resources for theFS segment register.If a segment is renamed, but not retiredand a second update to the same segmentoccurs, a stall occurs in the front-end ofthe pipeline until the renamed segmentretires.D4H08HSEG_RENAME_STALLS.GSSegmentrename stalls GSThis event counts the number of stalls dueto the lack of renaming resources for theGS segment register.If a segment is renamed, but not retiredand a second update to the same segmentoccurs, a stall occurs in the front-end ofthe pipeline until the renamed segmentretires.D4HD5H0FH01HA-42 Vol.
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