Volume 3B System Programming Guide_ Part 2 (794104), страница 80
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3DescriptionCommentUse Cmask =1to countduration.PERFORMANCE-MONITORING EVENTSTable A-4. Non-Architectural Performance Eventsin Intel Core Solo and Intel Core Duo Processors (Contd.)EventNum.Event MaskMnemonicUmaskValueDescriptionComment4FHL1_Pref_Req00HL1 prefetch requests due to DCUcache missesMay overcountif request resubmitted60HBus_Req_Outstanding00; Requirescorespecificity,and agentspecificityWeighted cycles of cacheable busdata read requests. This eventcounts full-line read request fromDCU or HW prefetcher, but notRFO, write, instruction fetches, orothers.Use Cmask =1to countduration.Use Umask bit12 to includeHWP or excludeHWP separately.61HBus_BNR_Clocks00HExternal bus cycles while BNRasserted62HBus_DRDY_Clocks00HExternal bus cycles while DRDYassertedRequires agentspecificity63HBus_Locks_Clocks00HExternal bus cycles while bus locksignal assertedRequires corespecificity64HBus_Data_Rcv40HExternal bus cycles while bus locksignal asserted65HBus_Trans_BrdSee comment.
Burst read bus transactions (dataor code)Requires corespecificity66HBus_Trans_RFOSee comment. Completed read for ownership(RFO) transactionsRequires agentspecificity68HBus_Trans_IfetchSee comment. Completed instruction fetchtransactionsRequires corespecificity69HBus_Trans_InvalSee comment. Completed invalidate transactions6AHBus_Trans_PwrSee comment.
Completed partial writetransactions6BHBus_Trans_PEachtransactioncounts itsaddress strobe6CHBus_Trans_IOSee comment. Completed partial transactionsRetried(include partial read + partial write transaction may+ line write)be countedmore than onceSee comment. Completed I/O transactions (readand write)Vol. 3 A-49PERFORMANCE-MONITORING EVENTSTable A-4.
Non-Architectural Performance Eventsin Intel Core Solo and Intel Core Duo Processors (Contd.)EventNum.Event MaskMnemonicUmaskValueDescriptionComment6DHBus_Trans_Def20HCompleted defer transactionsRequires corespecificityRetriedtransaction maybe countedmore than once67HBus_Trans_WBC0HCompleted writeback transactionsfrom DCU (does not include L2writebacks)6EHBus_Trans_BurstC0HCompleted burst transactions (fullline transactions include reads,write, RFO, and writebacks)6FHBus_Trans_MemC0HCompleted memory transactions.This includes Bus_Trans_Burst +Bus_Trans_P+Bus_Trans_Inval.70HBus_Trans_AnyC0HAny completed bus transactions77HBus_Snoops00HExternal bus cycles while bus locksignal assertedRequires agentspecificityEachtransactioncounts itsaddress strobeRetriedtransaction maybe countedmore than onceRequires MESIqualificationRequires agentspecificity78HDCU_Snoop_To_Share01HDCU snoops to share-state L1cache line due to L1 missesRequires corespecificity7DHBus_Not_In_Use00HNumber of cycles there is notransaction from the coreRequires corespecificity7EHBus_Snoop_Stall00HNumber of bus cycles while bussnoop is stalled80HICache_Reads00HNumber of instruction fetchesfrom ICache, streaming buffers(both cacheable and uncacheablefetches)81HICache_Misses00HNumber of instruction fetch missesfrom ICache, streaming buffers.85HITLB_Misses00HNumber of iITLB misses86HIFU_Mem_Stall00HCycles IFU is stalled while waitingfor data from memoryA-50 Vol.
3PERFORMANCE-MONITORING EVENTSTable A-4. Non-Architectural Performance Eventsin Intel Core Solo and Intel Core Duo Processors (Contd.)EventNum.Event MaskMnemonicUmaskValue87HILD_Stall00HNumber of instruction lengthdecoder stalls (Counts number ofLCP stalls)88HBr_Inst_Exec00HBranch instruction executed(includes speculation).89HBr_Missp_Exec00HBranch instructions executed andmispredicted at execution(includes branches that do nothave prediction or mispredicted)8AHBr_BAC_Missp_Exec00HBranch instructions executed thatwere mispredicted at front end8BHBr_Cnd_Exec00HConditional branch instructionsexecuted8CHBr_Cnd_Missp_Exec00HConditional branch instructionsexecuted that were mispredicted8DHBr_Ind_Exec00HIndirect branch instructionsexecuted8EHBr_Ind_Missp_Exec00HIndirect branch instructionsexecuted that were mispredicted8FHBr_Ret_Exec00HReturn branch instructionsexecuted90HBr_Ret_Missp_Exec00HReturn branch instructionsexecuted that were mispredicted91HBr_Ret_BAC_Missp_Exec00HReturn branch instructionsexecuted that were mispredictedat the front end92HBr_Call_Exec00HReturn call instructions executed93HBr_Call_Missp_Exec00HReturn call instructions executedthat were mispredicted94HBr_Ind_Call_Exec00HIndirect call branch instructionsexecutedA2HResource_Stall00HCycles while there is a resourcerelated stall (renaming, bufferentries) as seen by allocatorB0HMMX_Instr_Exec00HNumber of MMX instructionsexecuted (does not include MOVQand MOVD stores)DescriptionCommentVol.
3 A-51PERFORMANCE-MONITORING EVENTSTable A-4. Non-Architectural Performance Eventsin Intel Core Solo and Intel Core Duo Processors (Contd.)EventNum.Event MaskMnemonicUmaskValueB1HSIMD_Int_Sat_Exec00HNumber of SIMD Integer saturatinginstructions executedB3HSIMD_Int_Pmul_Exec01HNumber of SIMD Integer packedmultiply instructions executedB3HSIMD_Int_Psft_Exec02HNumber of SIMD Integer packedshift instructions executedB3HSIMD_Int_Pck_Exec04HNumber of SIMD Integer packoperations instruction executedB3HSIMD_Int_Upck_Exec08HNumber of SIMD Integer unpackinstructions executedB3HSIMD_Int_Plog_Exec10HNumber of SIMD Integer packedlogical instructions executedB3HSIMD_Int_Pari_Exec20HNumber of SIMD Integer packedarithmetic instructions executedC0HInstr_Ret00HNumber of instruction retired(Macro fused instruction countas 2)C1HFP_Comp_Instr_Ret00HNumber of FP computeinstructions retired (X87instruction or instruction thatcontain X87 operations)C2HUops_Ret00HNumber of micro-ops retired(include fused uops)C3HSMC_Detected00HNumber of times self-modifyingcode condition detectedC4HBr_Instr_Ret00HNumber of branch instructionsretiredC5HBr_MisPred_Ret00HNumber of mispredicted branchinstructions retiredC6HCycles_Int_Masked00HCycles while interrupt is disabledC7HCycles_Int_Pedning_ 00HMaskedCycles while interrupt is disabledand interrupts are pendingC8HHW_Int_Rx00HNumber of hardware interruptsreceivedC9HBr_Taken_Ret00HNumber of taken branchinstruction retiredA-52 Vol.
3DescriptionCommentPERFORMANCE-MONITORING EVENTSTable A-4. Non-Architectural Performance Eventsin Intel Core Solo and Intel Core Duo Processors (Contd.)EventNum.Event MaskMnemonicUmaskValueCAHBr_MisPred_Taken_Ret00HNumber of taken and mispredictedbranch instructions retiredCCHMMX_FP_Trans00HNumber of transitions from MMXto X87CCHFP_MMX_Trans01HNumber of transitions from X87 toMMXCDHMMX_Assist00HNumber of EMMS executedCEHMMX_Instr_Ret00HNumber of MMX instruction retiredDescriptionD0HInstr_Decoded00HNumber of instruction decodedD7HESP_Uops00HNumber of ESP folding instructiondecodedD8HSIMD_FP_SP_Ret00HNumber of SSE/SSE2 singleprecision instructions retired(packed and scalar)D8HSIMD_FP_SP_S_Ret01HNumber of SSE/SSE2 scalar singleprecision instructions retiredD8HSIMD_FP_DP_P_Ret02HNumber of SSE/SSE2 packeddouble precision instructionsretiredD8HSIMD_FP_DP_S_Ret03HNumber of SSE/SSE2 scalar doubleprecision instructions retiredD8HSIMD_Int_128_Ret04HNumber of SSE2 128 bit integerinstructions retiredD9HSIMD_FP_SP_P_Comp_Ret00HNumber of SSE/SSE2 packed singleprecision compute instructionsretired (does not include AND, OR,XOR)D9HSIMD_FP_SP_S_Comp_Ret01HNumber of SSE/SSE2 scalar singleprecision compute instructionsretired (does not include AND, OR,XOR)D9HSIMD_FP_DP_P_Comp_Ret02HNumber of SSE/SSE2 packeddouble precision computeinstructions retired (does notinclude AND, OR, XOR)CommentVol.
3 A-53PERFORMANCE-MONITORING EVENTSTable A-4. Non-Architectural Performance Eventsin Intel Core Solo and Intel Core Duo Processors (Contd.)EventNum.Event MaskMnemonicUmaskValueD9HSIMD_FP_DP_S_Comp_Ret03HNumber of SSE/SSE2 scalar doubleprecision compute instructionsretired (does not include AND, OR,XOR)DAHFused_Uops_Ret00HAll fused uops retiredDAHFused_Ld_Uops_Ret01HFused load uops retiredDAHFused_St_Uops_Ret02HFused store uops retiredDBHUnfusion00HNumber of unfusion events in theROB (due to exception)E0HBr_Instr_Decoded00HBranch instructions decodedE2HBTB_Misses00HNumber of branches the BTB didnot produce a predictionE4HBr_Bogus00HNumber of bogus branchesE6HBAClears00HNumber of BAClears assertedF0HPref_Rqsts_Up00HNumber of hardware prefetchrequests issued in forwardstreamsF8HPref_Rqsts_Dn00HNumber of hardware prefetchrequests issued in backwardstreamsA.4DescriptionCommentPENTIUM 4 AND INTEL XEON PROCESSORPERFORMANCE-MONITORING EVENTSTables A-5, A-6 and list performance-monitoring events that can be counted orsampled on processors based on Intel NetBurst microarchitecture.
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