Volume 3B System Programming Guide_ Part 2 (794104), страница 82
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or changethe access result status (hit,miss) as seen by this event.IOQ_allocationA-62 Vol. 3This event counts the varioustypes of transactions on the bus.A count is generated each time atransaction is allocated into theIOQ that matches the specifiedmask bits. An allocated entry canbe a sector (64 bytes) or a chunksof 8 bytes.PERFORMANCE-MONITORING EVENTSTable A-5. Performance Monitoring Events Supported by Intel NetBurstMicroarchitecture for Non-Retirement Counting (Contd.)Event NameEvent ParametersParameter ValueDescriptionRequests are counted once perretry.
The event mask bitsconstitute 4 bit fields. Atransaction type is specified byinterpreting the values of each bitfield.Specify one or more event maskbits in a bit field to select thevalue of the bit field.Each field (bits 0-4 are one field)are independent of and can beORed with the others. Therequest type field is furthercombined with bit 5 and 6 to forma binary expression. Bits 7 and 8form a bit field to specify thememory type of the targetaddress.Bits 13 and 14 form a bit field tospecify the source agent of therequest. Bit 15 affects readoperation only. The event istriggered by evaluating the logicalexpression: (((Request type) ORBit 5 OR Bit 6) OR (Memory type))AND (Source agent).ESCR restrictionsMSR_FSB_ESCR0,MSR_FSB_ESCR1Counter numbersper ESCRESCR0: 0, 1;ESCR Event Select03HESCR1: 2, 3ESCR[31:25]Vol.
3 A-63PERFORMANCE-MONITORING EVENTSTable A-5. Performance Monitoring Events Supported by Intel NetBurstMicroarchitecture for Non-Retirement Counting (Contd.)Event NameEvent ParametersParameter ValueDescriptionESCR[24:9]ESCR Event MaskBitsCCCR SelectEvent SpecificNotes0-4 (single field)Bus request type (use 00001 forinvalid or default)5: ALL_READCount read entries6: ALL_WRITECount write entries7: MEM_UCCount UC memory access entries8: MEM_WCCount WC memory access entries9: MEM_WTCount write-through (WT)memory access entries.10: MEM_WPCount write-protected (WP)memory access entries11: MEM_WBCount WB memory access entries.13: OWNCount all store requests driven byprocessor, as opposed to otherprocessor or DMA.14: OTHERCount all requests driven by otherprocessors or DMA.15: PREFETCHInclude HW and SW prefetchrequests in the count.06HCCCR[15:13]1: If PREFETCH bit is cleared,sectors fetched using prefetchare excluded in the counts.
IfPREFETCH bit is set, all sectorsor chunks read are counted.2: Specify the edge trigger inCCCR to avoid double counting.A-64 Vol. 3PERFORMANCE-MONITORING EVENTSTable A-5. Performance Monitoring Events Supported by Intel NetBurstMicroarchitecture for Non-Retirement Counting (Contd.)Event NameEvent ParametersParameter ValueDescription3: The mapping of interpreted bitfield values to transactiontypes may differ with differentprocessor modelimplementations of thePentium 4 processor family.Applications that programperformance monitoringevents should use CPUID todetermine processor modelswhen using this event.
Thelogic equations that trigger theevent are model-specific (see4a and 4b below).4a:For Pentium 4 and XeonProcessors starting with CPUIDModel field encoding equal to 2or greater, this event istriggered by evaluating thelogical expression ((Requesttype) and (Bit 5 or Bit 6) and(Memory type) and (Sourceagent)).4b:For Pentium 4 and XeonProcessors with CPUID Modelfield encoding less than 2, thisevent is triggered byevaluating the logicalexpression [((Request type) orBit 5 or Bit 6) or (Memorytype)] and (Source agent).
Notethat event mask bits formemory type are ignored ifeither ALL_READ orALL_WRITE is specified.Vol. 3 A-65PERFORMANCE-MONITORING EVENTSTable A-5. Performance Monitoring Events Supported by Intel NetBurstMicroarchitecture for Non-Retirement Counting (Contd.)Event NameEvent ParametersParameter ValueDescription5: This event is known to ignoreCPL in early implementationsof Pentium 4 and XeonProcessors. Both user requestsand OS requests are included inthe count. This behavior isfixed starting with Pentium 4and Xeon Processors withCPUID signature 0xF27 (Family15, Model 2, Stepping 7).6: For write-through (WT) andwrite-protected (WP) memorytypes, this event counts readsas the number of 64-bytesectors. Writes are counted byindividual chunks.7: For uncacheable (UC) memorytypes, this events counts thenumber of 8-byte chunksallocated.8: For Pentium 4 and XeonProcessors with CPUIDSignature less than 0xf27, onlyMSR_FSB_ESCR0 is available.IOQ_active_entriesThis event counts the number ofentries (clipped at 15) in the IOQthat are active.
An allocated entrycan be a sector (64 bytes) or achunks of 8 bytes.The event must be programmed inconjunction with IOQ_allocation.Specify one or more event maskbits to select the transactionsthat is counted.A-66 Vol. 3ESCR restrictionsMSR_FSB_ESCR1Counter numbersper ESCRESCR1: 2, 3ESCR Event Select01AHESCR[30:25]PERFORMANCE-MONITORING EVENTSTable A-5. Performance Monitoring Events Supported by Intel NetBurstMicroarchitecture for Non-Retirement Counting (Contd.)Event NameEvent ParametersParameter ValueDescriptionESCR[24:9]ESCR Event MaskBitsCCCR SelectEvent SpecificNotes0-4 (single field)Bus request type (use 00001 forinvalid or default).5: ALL_READCount read entries.6: ALL_WRITECount write entries.7: MEM_UCCount UC memory access entries.8: MEM_WCCount WC memory access entries.9: MEM_WTCount write-through (WT)memory access entries.10: MEM_WPCount write-protected (WP)memory access entries.11: MEM_WBCount WB memory access entries.13: OWNCount all store requests driven byprocessor, as opposed to otherprocessor or DMA.14: OTHERCount all requests driven by otherprocessors or DMA.15: PREFETCHInclude HW and SW prefetchrequests in the count.06HCCCR[15:13]1: Specified desired mask bits inESCR0 and ESCR1.2: See the ioq_allocation eventfor descriptions of the maskbits.3: Edge triggering should not beused when counting cycles.Vol.
3 A-67PERFORMANCE-MONITORING EVENTSTable A-5. Performance Monitoring Events Supported by Intel NetBurstMicroarchitecture for Non-Retirement Counting (Contd.)Event NameEvent ParametersParameter ValueDescription4: The mapping of interpreted bitfield values to transactiontypes may differ acrossdifferent processor modelimplementations of thePentium 4 processor family.Applications that programsperformance monitoringevents should use the CPUIDinstruction to detect processormodels when using this event.The logical expression thattriggers this event as describebelow:5a:For Pentium 4 and XeonProcessors starting with CPUIDMODEL field encoding equal to2 or greater, this event istriggered by evaluating thelogical expression ((Requesttype) and (Bit 5 or Bit 6) and(Memory type) and (Sourceagent)).5b:For Pentium 4 and XeonProcessors starting with CPUIDMODEL field encoding less than2, this event is triggered byevaluating the logicalexpression [((Request type) orBit 5 or Bit 6) or (Memorytype)] and (Source agent).Event mask bits for memorytype are ignored if eitherALL_READ or ALL_WRITE isspecified.5c: This event is known to ignoreCPL in the currentimplementations of Pentium 4and Xeon Processors Both userrequests and OS requests areincluded in the count.A-68 Vol.
3PERFORMANCE-MONITORING EVENTSTable A-5. Performance Monitoring Events Supported by Intel NetBurstMicroarchitecture for Non-Retirement Counting (Contd.)Event NameEvent ParametersParameter ValueDescription6: An allocated entry can be a fullline (64 bytes) or in individualchunks of 8 bytes.FSB_data_activityThis event increments once foreach DRDY or DBSY event thatoccurs on the front side bus. Theevent allows selection of aspecific DRDY or DBSY event.ESCR restrictionsMSR_FSB_ESCR0MSR_FSB_ESCR1Counter numbersper ESCRESCR0: 0, 1ESCR Event Select17HESCR1: 2, 3ESCR Event MaskESCR[31:25]ESCR[24:9]Bit 0:DRDY_DRVCount when this processor drivesdata onto the bus - includeswrites and implicit writebacks.Asserted two processor clockcycles for partial writes and 4processor clocks (usually inconsecutive bus clocks) for fullline writes.1: DRDY_OWNCount when this processor readsdata from the bus - includes loadsand some PIC transactions.Asserted two processor clockcycles for partial reads and 4processor clocks (usually inconsecutive bus clocks) for fullline reads.Count DRDY events that we drive.Count DRDY events sampled thatwe own.Vol.
3 A-69PERFORMANCE-MONITORING EVENTSTable A-5. Performance Monitoring Events Supported by Intel NetBurstMicroarchitecture for Non-Retirement Counting (Contd.)Event NameEvent ParametersParameter ValueDescription2: DRDY_OTHERCount when data is on the bus butnot being sampled by theprocessor.
It may or may not bebeing driven by this processor.Asserted two processor clockcycles for partial transactions and4 processor clocks (usually inconsecutive bus clocks) for fullline transactions.3: DBSY_DRVCount when this processorreserves the bus for use in thenext bus cycle in order to drivedata. Asserted for two processorclock cycles for full line writes andnot at all for partial line writes.May be asserted multiple times (inconsecutive bus clocks) if we stallthe bus waiting for a cache lock tocomplete.4: DBSY_OWNCount when some agent reservesthe bus for use in the next buscycle to drive data that thisprocessor will sample.Asserted for two processor clockcycles for full line writes and notat all for partial line writes. May beasserted multiple times (all onebus clock apart) if we stall the busfor some reason.5:DBSY_OTHERCount when some agent reservesthe bus for use in the next buscycle to drive data that thisprocessor will NOT sample.
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