Volume 3B System Programming Guide_ Part 2 (794104), страница 86
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3 A-95PERFORMANCE-MONITORING EVENTSTable A-10. List of Metrics Available for Replay Tagging(For Replay Event Only) (Contd.)Event MaskValue forReplay_eventIA32_PEBS_ENABLE Fieldto SetMSR_PEBS_MATRIX_VERTBit Field to Setsplit_load_retiredBit 10, Bit 24,Bit 25Bit 0Selectload_port_replayevent with theMSR_SAAT_ESCR1MSR and set theSPLIT_LD mask bit.NBOGUSsplit_store_retiredBit 10, Bit 24,Bit 25Bit 1Selectstore_port_replayevent with theMSR_SAAT_ESCR0MSR and set theSPLIT_ST mask bit.NBOGUSReplay metric1Additional MSR/EventNOTES:1.
Certain kinds of μops cannot be tagged. These include I/O operations, UC and locked accesses,returns, and far transfers.2. 2nd-level misses retired does not count all 2nd-level misses. It only includes those references thatare found to be misses by the fast detection logic and not those that are later found to be misses.3. While there are several causes for a MOB replay, the event counted with this event mask setting isthe case where the data from a load that would otherwise be forwarded is not an aligned subset ofthe data from a preceding store.A-96 Vol. 3PERFORMANCE-MONITORING EVENTSTable A-11. Event Mask Qualification for Logical ProcessorsEvent TypeEvent NameEvent Masks, ESCR[24:9]Non-RetirementBPU_fetch_requestBit 0: TCMISSNon-RetirementBSQ_allocationNon-RetirementBSQ_cache_referenceBitTS or TITS0: REQ_TYPE0TS1: REQ_TYPE1TS2: REQ_LEN0TS3: REQ_LEN1TS5: REQ_IO_TYPETS6: REQ_LOCK_TYPETS7: REQ_CACHE_TYPETS8: REQ_SPLIT_TYPETS9: REQ_DEM_TYPETS10: REQ_ORD_TYPETS11: MEM_TYPE0TS12: MEM_TYPE1TS13: MEM_TYPE2TSBit0: RD_2ndL_HITSTS1: RD_2ndL_HITETS2: RD_2ndL_HITMTS3: RD_3rdL_HITSTS4: RD_3rdL_HITETS5: RD_3rdL_HITMTS6: WR_2ndL_HITTS7: WR_3rdL_HITTS8: RD_2ndL_MISSTS9: RD_3rdL_MISSTS10: WR_2ndL_MISSTS11: WR_3rdL_MISSTSVol.
3 A-97PERFORMANCE-MONITORING EVENTSTable A-11. Event Mask Qualification for Logical Processors (Contd.)Event TypeEvent NameNon-Retirementmemory_cancelEvent Masks, ESCR[24:9]BitTS or TI2: ST_RB_FULLTS3: 64K_CONFTSNon-RetirementSSE_input_assistBit 15: ALLTINon-Retirement64bit_MMX_uopBit 15: ALLTINon-Retirementpacked_DP_uopBit 15: ALLTINon-Retirementpacked_SP_uopBit 15: ALLTINon-Retirementscalar_DP_uopBit 15: ALLTINon-Retirementscalar_SP_uopBit 15: ALLTINon-Retirement128bit_MMX_uopBit 15: ALLTINon-Retirementx87_FP_uopBit 15: ALLTINon-Retirementx87_SIMD_moves_uopBitNon-RetirementNon-RetirementA-98 Vol. 3FSB_data_activityIOQ_allocation3: ALLP0TI4: ALLP2TIBit0: DRDY_DRVTI1: DRDY_OWNTI2: DRDY_OTHERTI3: DBSY_DRVTI4: DBSY_OWNTI5: DBSY_OTHERTIBit0: ReqA0TS1: ReqA1TS2: ReqA2TS3: ReqA3TS4: ReqA4TS5: ALL_READTS6: ALL_WRITETS7: MEM_UCTS8: MEM_WCTSPERFORMANCE-MONITORING EVENTSTable A-11.
Event Mask Qualification for Logical Processors (Contd.)Event TypeNon-RetirementEvent NameIOQ_active_entriesEvent Masks, ESCR[24:9]TS or TI9: MEM_WTTS10: MEM_WPTS11: MEM_WBTS13: OWNTS14: OTHERTS15: PREFETCHTSBitTS0: ReqA01:ReqA1TS2: ReqA2TS3: ReqA3TS4: ReqA4TS5: ALL_READTS6: ALL_WRITETS7: MEM_UCTS8: MEM_WCTS9: MEM_WTTS10: MEM_WPTS11: MEM_WBTS13: OWNTS14: OTHERTS15: PREFETCHTSTSNon-Retirementglobal_power_eventsBit 0: RUNNINGNon-RetirementITLB_referenceBit0: HITTS1: MISSTS2: HIT_UCTSVol. 3 A-99PERFORMANCE-MONITORING EVENTSTable A-11. Event Mask Qualification for Logical Processors (Contd.)Event TypeEvent NameEvent Masks, ESCR[24:9]Non-RetirementMOB_load_replayBitNon-RetirementNon-Retirementpage_walk_typeuop_typeTS or TI1: NO_STATS3: NO_STDTS4: PARTIAL_DATATS5: UNALGN_ADDRTSBit0: DTMISSTI1: ITMISSTIBit1: TAGLOADSTS2: TAGSTORESTSNon-Retirementload_port_replayBit 1: SPLIT_LDTSNon-Retirementstore_port_replayBit 1: SPLIT_STTSNon-Retirementmemory_completeNon-RetirementNon-RetirementA-100 Vol.
3retired_mispred_branch_typeretired_branch_typeBit0: LSCTS1: SSCTS2: USCTS3: ULCTSBit0: UNCONDITIONALTS1: CONDITIONALTS2: CALLTS3: RETURNTS4: INDIRECTTSBit0: UNCONDITIONALTS1: CONDITIONALTS2: CALLTS3: RETURNTS4: INDIRECTTSPERFORMANCE-MONITORING EVENTSTable A-11. Event Mask Qualification for Logical Processors (Contd.)Event TypeEvent NameNon-Retirementtc_ms_xferEvent Masks, ESCR[24:9]Bit0: CISCNon-Retirementtc_miscBit4: FLUSHNon-RetirementNon-RetirementTC_deliver_modeuop_queue_writesNon-Retirementresource_stallNon-RetirementWC_BufferAt Retirementinstr_retiredBitTS or TITSTS0: DDTI1: DBTI2: DITI3: BDTI4: BBTI5: BITI6: IDTI7: IBTIBit0: FROM_TC_BUILDTS1: FROM_TC_DELIVERTS2: FROM_ROMTSBit 5: SBFULLTSBitTI0: WCB_EVICTSTI1: WCB_FULL_EVICTTI2: WCB_HITM_EVICTTIBit0: NBOGUSNTAGTS1: NBOGUSTAGTS2: BOGUSNTAGTS3: BOGUSTAGTSVol.
3 A-101PERFORMANCE-MONITORING EVENTSTable A-11. Event Mask Qualification for Logical Processors (Contd.)Event TypeEvent NameEvent Masks, ESCR[24:9]At Retirementmachine_clearBitAt RetirementAt RetirementAt RetirementAt RetirementAt RetirementAt RetirementA-102 Vol. 3front_end_eventreplay_eventexecution_eventx87_assistbranch_retiredmispred_branch_retiredTS or TI0: CLEARTS2: MOCLEARTS6: SMCCLEARTSBit0: NBOGUSTS1: BOGUSTSBit0: NBOGUSTS1: BOGUSTSBit0: NONBOGUS0TS1: NONBOGUS1TS2: NONBOGUS2TS3: NONBOGUS3TS4: BOGUS0TS5: BOGUS1TS6: BOGUS2TS7: BOGUS3TSBit0: FPSUTS1: FPSOTS2: POAOTS3: POAUTS4: PREATSBit0: MMNPTS1: MMNMTS2: MMTPTS3: MMTMTSBit 0: NBOGUSTSPERFORMANCE-MONITORING EVENTSTable A-11.
Event Mask Qualification for Logical Processors (Contd.)Event TypeEvent NameAt Retirementuops_retiredAt RetirementA.5Event Masks, ESCR[24:9]TS or TIBitinstr_completed0: NBOGUSTS1: BOGUSTSBit0: NBOGUSTS1: BOGUSTSPERFORMANCE MONITORING EVENTS FORINTEL® PENTIUM® M PROCESSORSThe Pentium M processor’s performance-monitoring events are based on monitoringevents for the P6 family of processors. All of these performance events are modelspecific for the Pentium M processor and are not available in this form in otherprocessors. Table A-12 lists the Performance-Monitoring events that were added inthe Pentium M processor.Table A-12. Performance Monitoring Events on Intel® Pentium® MProcessorsNameHex ValuesDescriptions58HNumber of Enhanced Intel SpeedSteptechnology transitions:Power ManagementEMON_EST_TRANSMask = 00H - All transitionsMask = 02H - Only FrequencytransitionsEMON_THERMAL_TRIP59HDuration/Occurrences in thermal trip; tocount number of thermal trips: bit 22 inPerfEvtSel0/1 needs to be set to enableedge detect.BR_INST_EXEC88HBranch instructions that were executed(not necessarily retired).BR_MISSP_EXEC89HBranch instructions executed that weremispredicted at execution.BPUVol.
3 A-103PERFORMANCE-MONITORING EVENTSTable A-12. Performance Monitoring Events on Intel® Pentium® MProcessors (Contd.)NameHex ValuesDescriptionsBR_BAC_MISSP_EXEC8AHBranch instructions executed that weremispredicted at front end (BAC).BR_CND_EXEC8BHConditional branch instructions thatwere executed.BR_CND_MISSP_EXEC8CHConditional branch instructionsexecuted that were mispredicted.BR_IND_EXEC8DHIndirect branch instructions executed.BR_IND_MISSP_EXEC8EHIndirect branch instructions executedthat were mispredicted.BR_RET_EXEC8FHReturn branch instructions executed.BR_RET_MISSP_EXEC90HReturn branch instructions executedthat were mispredicted at execution.BR_RET_BAC_MISSP_EXEC91HReturn branch instructions executedthat were mispredicted at front end(BAC).BR_CALL_EXEC92HCALL instruction executed.BR_CALL_MISSP_EXEC93HCALL instruction executed and misspredicted.BR_IND_CALL_EXEC94HIndirect CALL instructions executed.EMON_SIMD_INSTR_RETIREDCEHNumber of retired MMX instructions.EMON_SYNCH_UOPSD3HSync micro-opsEMON_ESP_UOPSD7HTotal number of micro-opsEMON_FUSED_UOPS_RETDAHNumber of retired fused micro-ops:DecoderMask = 0 - Fused micro-opsMask = 1 - Only load+Op micro-opsMask = 2 - Only std+sta micro-opsEMON_UNFUSIONA-104 Vol.
3DBHNumber of unfusion events in the ROB,happened on a FP exception to a fusedµop.PERFORMANCE-MONITORING EVENTSTable A-12. Performance Monitoring Events on Intel® Pentium® MProcessors (Contd.)NameHex ValuesDescriptionsEMON_PREF_RQSTS_UPF0HNumber of upward prefetches issuedEMON_PREF_RQSTS_DNF8HNumber of downward prefetches issuedPrefetcherA number of P6 family processor performance monitoring events are modified for thePentium M processor. Table A-13 lists the performance monitoring events that werechanged in the Pentium M processor, and differ from performance monitoring eventsfor the P6 family of processors.Table A-13. Performance Monitoring Events Modified on Intel® Pentium® MProcessorsNameHexValuesDescriptionsCPU_CLK_UNHALTED79HNumber of cycles during which the processor is nothalted, and not in a thermal trip.EMON_SSE_SSE2_INST_RETIREDD8HStreaming SIMD Extensions Instructions Retired:Mask = 0 – SSE packed single and scalar singleMask = 1 – SSE scalar-singleMask = 2 – SSE2 packed-doubleMask = 3 – SSE2 scalar-doubleEMON_SSE_SSE2_COMP_INST_RETIREDD9HComputational SSE Instructions Retired:Mask = 0 – SSE packed singleMask = 1 – SSE Scalar-singleMask = 2 – SSE2 packed-doubleMask = 3 – SSE2 scalar-doubleVol.
3 A-105PERFORMANCE-MONITORING EVENTSTable A-13. Performance Monitoring Events Modified on Intel® Pentium® MProcessors (Contd.)NameHexValuesDescriptionsL2_LD29HL2 data loadsMask[0] = 1 – count I state linesL2_LINES_IN24HL2 linesallocatedMask[1] = 1 – count S statelinesL2_LINES_OUT26HL2 lines evictedL2_M_LINES_OUT27HLw M-state linesevictedMask[2] = 1 – count E statelinesMask[3] = 1 – count M statelinesMask[5:4]:00H – Excluding hardwareprefetched lines01H - Hardware-prefetchedlines only02H/03H – All (HW-prefetchedlines and non HW --Prefetchedlines)A.6P6 FAMILY PROCESSOR PERFORMANCEMONITORING EVENTSTable A-14 lists the events that can be counted with the performance-monitoringcounters and read with the RDPMC instruction for the P6 family processors.
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