Volume 3B System Programming Guide_ Part 2 (794104), страница 87
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The unitcolumn gives the microarchitecture or bus unit that produces the event; the eventnumber column gives the hexadecimal number identifying the event; the mnemonicevent name column gives the name of the event; the unit mask column gives the unitmask required (if any); the description column describes the event; and thecomments column gives additional information about the event.All of these performance events are model specific for the P6 family processors andare not available in this form in the Pentium 4 processors or the Pentium processors.Some events (such as those added in later generations of the P6 family processors)are only available in specific processors in the P6 family. All performance eventencodings not listed in Table A-14 are reserved and their use will result in undefinedcounter results.See the end of the table for notes related to certain entries in the table.A-106 Vol.
3PERFORMANCE-MONITORING EVENTSTable A-14. Events That Can Be Counted with the P6 Family PerformanceMonitoring CountersUnitData CacheUnit (DCU)Event Mnemonic EventNum. NameUnitMask43H00HDATA_MEM_REFSDescriptionCommentsAll loads from anymemory type. All storesto any memory type.Each part of a split iscounted separately.
Theinternal logic counts notonly memory loads andstores, but also internalretries.80-bit floating-pointaccesses are doublecounted, since they aredecomposed into a 16-bitexponent load and a64-bit mantissa load.Memory accesses areonly counted when theyare actually performed(such as a load that getssquashed because aprevious cache miss isoutstanding to the sameaddress, and which finallygets performed, is onlycounted once).Does not include I/Oaccesses, or othernonmemory accesses.45HDCU_LINES_IN00HTotal lines allocated inDCU46HDCU_M_LINES_IN00HNumber of M state linesallocated in DCU47HDCU_M_LINES_OUT00HNumber of M state linesevicted from DCUThis includes evictionsvia snoop HITM,intervention orreplacement.Vol.
3 A-107PERFORMANCE-MONITORING EVENTSTable A-14. Events That Can Be Counted with the P6 Family PerformanceMonitoring Counters (Contd.)UnitEvent Mnemonic EventNum. NameUnitMask48H00HDCU_MISS_OUTSTANDINGDescriptionCommentsWeighted number ofcycles while a DCU miss isoutstanding, incrementedby the number ofoutstanding cachemisses at any particulartime.An access that alsomisses the L2 isshort-changed by 2cycles (i.e., if countsN cycles, should beN+2 cycles).Cacheable read requestsonly are considered.Uncacheable requestsare excluded.Read-for-ownerships arecounted, as well as linefills, invalidates, andstores.InstructionFetch Unit(IFU)80HIFU_IFETCH00HNumber of instructionfetches, both cacheableand noncacheable,including UC fetches81HIFU_IFETCH_MISS00HNumber of instructionfetch missesAll instruction fetchesthat do not hit the IFU(i.e., that producememory requests).
Thisincludes UC accesses.85HITLB_MISS00HNumber of ITLB misses.86HIFU_MEM_STALL00HNumber of cyclesinstruction fetch isstalled, for any reason.Includes IFU cachemisses, ITLB misses, ITLBfaults, and other minorstalls.87HA-108 Vol. 3ILD_STALL00HNumber of cycles thatthe instruction lengthdecoder is stalled.Subsequent loadsto the same cacheline will not result inany additionalcounts.Count value notprecise, but stilluseful.PERFORMANCE-MONITORING EVENTSTable A-14.
Events That Can Be Counted with the P6 Family PerformanceMonitoring Counters (Contd.)Unit1L2 CacheEvent Mnemonic EventNum. NameUnitMaskDescription28HMESI0FHNumber of L2 instructionfetches.L2_IFETCHCommentsThis event indicates thata normal instructionfetch was received bythe L2.The count includes onlyL2 cacheable instructionfetches; it does notinclude UC instructionfetches.It does not include ITLBmiss accesses.29HL2_LDMESI0FHNumber of L2 data loads.This event indicates thata normal, unlocked, loadmemory access wasreceived by the L2.It includes only L2cacheable memoryaccesses; it does notinclude I/O accesses,other nonmemoryaccesses, or memoryaccesses such as UC/WTmemory accesses.It does include L2cacheable TLB missmemory accesses.2AHL2_STMESI0FHNumber of L2 datastores.This event indicates thata normal, unlocked, storememory access wasreceived by the L2.Vol. 3 A-109PERFORMANCE-MONITORING EVENTSTable A-14.
Events That Can Be Counted with the P6 Family PerformanceMonitoring Counters (Contd.)UnitEvent Mnemonic EventNum. NameUnitMaskDescriptionit indicates that the DCUsent a read-forownership request to theL2. It also includes Invalidto Modified requests sentby the DCU to the L2.It includes only L2cacheable memoryaccesses; it does notinclude I/O accesses,other nonmemoryaccesses, or memoryaccesses such as UC/WTmemory accesses.It includes TLB missmemory accesses.A-110 Vol. 324HL2_LINES_IN00HNumber of lines allocatedin the L2.26HL2_LINES_OUT00HNumber of lines removedfrom the L2 for anyreason.25HL2_M_LINES_INM00HNumber of modified linesallocated in the L2.27HL2_M_LINES_OUTM00HNumber of modified linesremoved from the L2 forany reason.2EHL2_RQSTSMESI0FHTotal number of L2requests.21HL2_ADS00HNumber of L2 addressstrobes.22HL2_DBUS_BUSY00HNumber of cycles duringwhich the L2 cache databus was busy.23HL2_DBUS_BUSY_RD00HNumber of cycles duringwhich the data bus wasbusy transferring readdata from L2 to theprocessor.CommentsPERFORMANCE-MONITORING EVENTSTable A-14.
Events That Can Be Counted with the P6 Family PerformanceMonitoring Counters (Contd.)UnitExternalBus Logic(EBL)2Event Mnemonic EventNum. NameUnitMask62H00H(Self)BUS_DRDY_CLOCKS20H(Any)63H60HBUS_LOCK_CLOCKSBUS_REQ_OUTSTANDINGDescriptionNumber of clocks during Unit Mask = 00Hwhich DRDY# is asserted. counts bus clocksUtilization of the external when the processoris driving DRDY#.system data bus duringdata transfers.Unit Mask = 20Hcounts in processorclocks when anyagent is drivingDRDY#.Always counts inprocessor clocks.20H(Any)Number of clocks duringwhich LOCK# is assertedon the external systembus.300H(Self)Number of bus requestsoutstanding.Counts only DCUfull-line cacheablereads, not RFOs,writes, instructionfetches, or anythingelse. Counts“waiting for bus tocomplete” (last datachunk received).00H(Self)This counter isincremented by thenumber of cacheableread bus requestsoutstanding in any givencycle.65HBUS_TRAN_BRDComments00H(Self)Number of burst readtransactions.20H(Any)66HBUS_TRAN_RFO00H(Self)20H(Any)67HBUS_TRANS_WB00H(Self)Number of completedread for ownershiptransactions.Number of completedwrite back transactions.20H(Any)Vol.
3 A-111PERFORMANCE-MONITORING EVENTSTable A-14. Events That Can Be Counted with the P6 Family PerformanceMonitoring Counters (Contd.)UnitEvent Mnemonic EventNum. NameUnitMask68H00H(Self)BUS_TRAN_IFETCH20H(Any)69HBUS_TRAN_INVAL00H(Self)DescriptionNumber of completedinstruction fetchtransactions.Number of completedinvalidate transactions.20H(Any)6AHBUS_TRAN_PWR00H(Self)20H(Any)6BHBUS_TRANS_P00H(Self)Number of completedpartial writetransactions.Number of completedpartial transactions.20H(Any)6CHBUS_TRANS_IO00H(Self)Number of completed I/Otransactions.20H(Any)6DHBUS_TRAN_DEF00H(Self)Number of completeddeferred transactions.20H(Any)6EHBUS_TRAN_BURST00H(Self)Number of completedburst transactions.20H(Any)70HBUS_TRAN_ANY00H(Self)Number of all completedbus transactions.20H(Any)Address bus utilizationcan be calculatedknowing the minimumaddress bus occupancy.Includes special cycles,etc.A-112 Vol.
3CommentsPERFORMANCE-MONITORING EVENTSTable A-14. Events That Can Be Counted with the P6 Family PerformanceMonitoring Counters (Contd.)UnitEvent Mnemonic EventNum. NameUnitMaskDescription6FH00H(Self)Number of completedmemory transactions.BUS_TRAN_MEMComments20H(Any)64HBUS_DATA_RCV00H(Self)Number of bus clockcycles during which thisprocessor is receivingdata.61HBUS_BNR_DRV00H(Self)Number of bus clockcycles during which thisprocessor is driving theBNR# pin.7AHBUS_HIT_DRV00H(Self)Number of bus clockcycles during which thisprocessor is driving theHIT# pin.Includes cycles dueto snoop stalls.The event countscorrectly, but BPMi(breakpointmonitor) pinsfunction as followsbased on thesetting of the PCbits (bit 19 in thePerfEvtSel0 andPerfEvtSel1registers):• If the core-clockto- bus-clockratio is 2:1 or 3:1,and a PC bit isset, the BPMipins will beasserted for asingle clock whenthe countersoverflow.Vol.
3 A-113PERFORMANCE-MONITORING EVENTSTable A-14. Events That Can Be Counted with the P6 Family PerformanceMonitoring Counters (Contd.)UnitEvent Mnemonic EventNum. NameUnitMaskDescriptionComments• If the PC bit isclear, theprocessortoggles the BPMipins when thecounteroverflows.• If the clock ratiois not 2:1 or 3:1,the BPMi pinswill not functionfor theseperformancemonitoringcounter events.7BHBUS_HITM_DRV00H(Self)Number of bus clockcycles during which thisprocessor is driving theHITM# pin.Includes cycles dueto snoop stalls.The event countscorrectly, but BPMi(breakpointmonitor) pinsfunction as followsbased on thesetting of the PCbits (bit 19 in thePerfEvtSel0 andPerfEvtSel1registers):• If the core-clockto- bus-clockratio is 2:1 or 3:1,and a PC bit isset, the BPMipins will beasserted for asingle clock whenthe countersoverflow.A-114 Vol.
3PERFORMANCE-MONITORING EVENTSTable A-14. Events That Can Be Counted with the P6 Family PerformanceMonitoring Counters (Contd.)UnitEvent Mnemonic EventNum. NameUnitMaskDescriptionComments• If the PC bit isclear, theprocessortoggles theBPMipins whenthe counteroverflows.• If the clock ratiois not 2:1 or 3:1,the BPMi pinswill not functionfor theseperformancemonitoringcounter events.FloatingPoint Unit7EHBUS_SNOOP_STALL00H(Self)Number of clock cyclesduring which the bus issnoop stalled.C1HFLOPS00HNumber of computationalfloating-point operationsretired.Counter 0 only.Excludes floating-pointcomputational operationsthat cause traps orassists.Includes floating-pointcomputational operationsexecuted by the assisthandler.Includes internal suboperations for complexfloating-pointinstructions liketranscendentals.Excludes floating-pointloads and stores.Vol.
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