Volume 3B System Programming Guide_ Part 2 (794104), страница 91
Текст из файла (страница 91)
(R/O)1 = Enabled0 = DisabledAlways 0 on the Pentium M processor.13In Order Queue Depth. (R/O)1=10=8141 MByte Power on Reset Vector. (R/O)1 = 1 MByte0 = 4 GBytesAlways 0 on the Pentium M processor.15Reserved17:16APIC Cluster ID. (R/O)Always 00B on the Pentium M processor.18System Bus Frequency. (R/O)0 = 100 MHz1 = ReservedAlways 0 on the Pentium M processor.19Reserved.21: 20Symmetric Arbitration ID. (R/O)Always 00B on the Pentium M processor.26:223AHB-4 Vol.
358IA32_FEATURE_CONTROLClock Frequency Ratio. (R/O)UniqueControl Features in IA-32 Processor. (R/W)(If CPUID.1:ECX.[bit 5] or CPUID.1:ECX.[bit 6] isset)MODEL-SPECIFIC REGISTERS (MSRS)Table B-1. MSRs in Processors Based on Intel Core Microarchitecture (Contd.)RegisterAddressHexDec40H64Register NameMSR_LASTBRANCH_0_FROM_IPShared/UniqueUniqueBit DescriptionLast Branch Record 0 From IP.
(R/W)One of four pairs of last branch recordregisters on the last branch record stack. Thispart of the stack contains pointers to thesource instruction for one of the last fourbranches, exceptions, or interrupts taken bythe processor. See also:• Last Branch Record Stack TOS at 1C9H• Section 18.8, “Last Branch, Interrupt, andException Recording (Pentium MProcessors).”41H42H43H60H61H62H63H65666796979899MSR_LASTBRANCH_1_FROM_IPUniqueMSR_LASTBRANCH_2_FROM_IPUniqueMSR_LASTBRANCH_3_FROM_IPUniqueMSR_LASTBRANCH_0_TO_LIPUniqueMSR_LASTBRANCH_1_TO_LIPUniqueMSR_LASTBRANCH_2_TO_LIPUniqueMSR_LASTBRANCH_3_TO_LIPUniqueLast Branch Record 1 From IP. (R/W)See description ofMSR_LASTBRANCH_0_FROM_IP.Last Branch Record 2 From IP.
(R/W)See description ofMSR_LASTBRANCH_0_FROM_IP.Last Branch Record 3 From IP. (R/W)See description ofMSR_LASTBRANCH_0_FROM_IP.Last Branch Record 0 To IP. (R/W)One of four pairs of last branch recordregisters on the last branch record stack.
Thispart of the stack contains pointers to thedestination instruction for one of the last fourbranches, exceptions, or interrupts taken bythe processor.Last Branch Record 1 To IP. (R/W)See description ofMSR_LASTBRANCH_0_TO_LIP.Last Branch Record 2 To IP. (R/W)See description ofMSR_LASTBRANCH_0_TO_LIP.Last Branch Record 3 To IP.
(R/W)See description ofMSR_LASTBRANCH_0_TO_LIP.Vol. 3 B-5MODEL-SPECIFIC REGISTERS (MSRS)Table B-1. MSRs in Processors Based on Intel Core Microarchitecture (Contd.)RegisterAddressRegister NameShared/UniqueBit DescriptionHexDec79H121IA32_BIOS_UPDT_TRIGUniqueBIOS Update Trigger Register. (R/W)8BH139IA32_BIOS_SIGN_IDUniqueBIOS Update Signature ID. (RO)C1H193IA32_PMC0UniquePerformance counter register.C2H194IA32_PMC1UniquePerformance counter register.CDH205MSR_FSB_FREQSharedScaleable Bus Speed(RO).This field indicates the scaleable bus clockspeed:2:0••••••101B: 100 MHz (FSB 400)001B: 133 MHz (FSB 533)011B: 167 MHz (FSB 667)010B: 200 MHz (FSB 800)000B: 267 MHz (FSB 1067)100B: 333 MHz (FSB 1333)133.33 MHz should be utilized if performingcalculation with System Bus Speed whenencoding is 101B.166.67 MHz should be utilized if performingcalculation with System Bus Speed whenencoding is 001B.266.67 MHz should be utilized if performingcalculation with System Bus Speed whenencoding is 000B.333.33 MHz should be utilized if performingcalculation with System Bus Speed whenencoding is 100B.63:3E7H231IA32_MPERF63:0ReservedUniqueMaximum Performance Frequency ClockCount.
(RW)C0_MCNT: C0 Maximum Frequency ClockCount.Increments at fixed interval when core is inC0.Cleared upon overflow/wrap-around ofIA32_APERF.B-6 Vol. 3MODEL-SPECIFIC REGISTERS (MSRS)Table B-1. MSRs in Processors Based on Intel Core Microarchitecture (Contd.)RegisterAddressHexDecE8H232Register NameIA32_APERFShared/UniqueUnique63:0Bit DescriptionActual Performance Frequency Clock Count.(RW)C0_ACNT: C0 Actual Frequency Clock Count.Accumulates core clock counts at thecoordinated clock frequency, when the core isin C0.Cleared upon overflow/wrap-around ofIA32_MPERF.FEH254IA32_MTRRCAPUnique11EH281MSR_BBL_CR_CTL3Shared0L2 Hardware Enabled. (RO)1 = If the L2 is hardware-enabled0 = Indicates if the L2 is hardware-disabled4:1Reserved.5ECC Check Enable.
(RO)This bit enables ECC checking on the cachedata bus. ECC is always generated on writecycles.0 = Disabled (default)1 = Enabled7:6Reserved.8L2 Enabled. (R/W)1 = L2 cache has been initialized0 = Disabled (default)Until this bit is set the processor will notrespond to the WBINVD instruction or theassertion of the FLUSH# input.22:9Reserved.23L2 Not Present. (RO)0 = L2 Present1 = L2 Not Present63:24Reserved.Vol. 3 B-7MODEL-SPECIFIC REGISTERS (MSRS)Table B-1. MSRs in Processors Based on Intel Core Microarchitecture (Contd.)RegisterAddressRegister NameShared/UniqueHexDec174H372IA32_SYSENTER_CSUnique175H373IA32_SYSENTER_ESPUnique176H374IA32_SYSENTER_EIPUnique179H377IA32_MCG_CAPUnique7:0Bit DescriptionCount. (RO)Indicates the number of hardware unit errorreporting banks available in the processor8IA32_MCG_CTL Present. (RO)1=0=63:917AH378IA32_MCG_STATUS0Indicates that the processor implementsthe MSR_MCG_CTL register found atMSR 17BH.Not supported.Reserved.UniqueRIPV.When set, bit indicates that the instructionaddressed by the instruction pointer pushedon the stack (when the machine check wasgenerated) can be used to restart theprogram.
If cleared, the program cannot bereliably restarted1EIPV.When set, bit indicates that the instructionaddressed by the instruction pointer pushedon the stack (when the machine check wasgenerated) is directly associated with theerror.B-8 Vol. 3MODEL-SPECIFIC REGISTERS (MSRS)Table B-1. MSRs in Processors Based on Intel Core Microarchitecture (Contd.)RegisterAddressHexRegister NameShared/UniqueBit DescriptionDec2MCIP.When set, bit indicates that a machine checkhas been generated.
If a second machinecheck is detected while this bit is still set, theprocessor enters a shutdown state. Softwareshould write this bit to 0 after processing amachine check exception.63:3Reserved.186H390IA32_PERFEVTSEL0Unique187H391IA32_PERFEVTSEL1Unique198H408IA32_PERF_STATShared198H40815:0Current Performance State Value.63:16Reserved.MSR_PERF_STATShared15:0Current Performance State Value.30:16Reserved.31XE Operation (R/O).If set, XE operation is enabled. Default iscleared.39:32Reserved.44:40Maximum Bus Ratio (R/O)Indicates maximum bus ratio configured forthe processor.63:45199H409IA32_PERF_CTLReserved.Unique15:0Target Performance State Value.31:16Reserved.32IDA Engage.
(R/W)When set to 1: disengages IDA.63:33Reserved.Vol. 3 B-9MODEL-SPECIFIC REGISTERS (MSRS)Table B-1. MSRs in Processors Based on Intel Core Microarchitecture (Contd.)RegisterAddressHexDec19AH410Register NameIA32_CLOCK_MODULATIONShared/UniqueUniqueBit DescriptionClock Modulation. (R/W)Enables and disables on-demand clockmodulation and allows the selection of the ondemand clock modulation duty cycle. SeeSection 13.5.3, “Software Controlled ClockModulation.”IA32_CLOCK_MODULATION MSR wasoriginally named IA32_THERM_CONTROLMSR.19BH411IA32_THERM_INTERRUPTUniqueThermal Interrupt Control.
(R/W)Enables and disables the generation of aninterrupt on temperature transitions detectedwith the processor’s thermal sensors andthermal monitor.See Section 13.5.2, “Thermal Monitor.”19CH412IA32_THERM_STATUSUniqueThermal Monitor Status. (R/W)Contains status information about theprocessor’s thermal sensor and automaticthermal monitoring facilities.See Section 13.5.2, “Thermal Monitor”.19DH413MSR_THERM2_CTLUnique15:0Reserved.16TM_SELECT. (R/W)Mode of automatic thermal monitor:0 = Thermal Monitor 1 (thermally-initiatedon-die modulation of the stop-clock dutycycle)1 = Thermal Monitor 2 (thermally-initiatedfrequency transitions)If bit 3 of the IA32_MISC_ENABLE register iscleared, TM_SELECT has no effect.
NeitherTM1 nor TM2 are enabled.63:16B-10 Vol. 3Reserved.MODEL-SPECIFIC REGISTERS (MSRS)Table B-1. MSRs in Processors Based on Intel Core Microarchitecture (Contd.)RegisterAddressHexDec1A0416Register NameShared/UniqueBit DescriptionIA32_MISC_ENABLEEnable Misc. Processor Features.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
