Volume 3B System Programming Guide_ Part 2 (794104), страница 76
Текст из файла (страница 76)
Thisincludes uncacheable fetches.An instruction fetch miss is counted onlyonce and not once for every cycle it isoutstanding.82H02HITLB.SMALL_MISSITLB small page This event counts the number ofmissesinstruction fetches from small pages thatmiss the ITLB.82H10HITLB.LARGE_MISSITLB large page This event counts the number ofmissesinstruction fetches from large pages thatmiss the ITLB.82H40HITLB.FLUSHITLB flushesThis event counts the number of ITLBflushes.
This usually happens upon CR3 orCR0 writes, which are executed by theoperating system during process switches.82H12HITLB.MISSESITLB missesThis event counts the number ofinstruction fetches from either small orlarge pages that miss the ITLB.83H02HINST_QUEUE.FULL Cycles duringwhich theinstructionqueue is fullThis event counts the number of cyclesduring which the instruction queue is full.In this situation, the core front-end stopsfetching more instructions. This is anindication of very long stalls in the backend pipeline stages.86H00HCYCLES_L1I_MEM_STALLEDThis event counts the number of cycles forwhich an instruction fetch stalls, includingstalls due to any of the following reasons:Cycles duringwhichinstructionfetches stalled• instruction Fetch Unit cache misses• instruction TLB misses• instruction TLB faultsVol.
3 A-25PERFORMANCE-MONITORING EVENTSTable A-3. Non-Architectural Performance Eventsin Processors Based on Intel Core Microarchitecture (Contd.)EventNumUmaskValueEvent NameDefinition87H00HILD_STALLInstructionLength Decoderstall cycles dueto a lengthchanging prefixDescription andCommentThis event counts the number of cyclesduring which the instruction lengthdecoder uses the slow length decoder.Usually, instruction length decoding isdone in one cycle. When the slow decoderis used, instruction decoding requires 6cycles.The slow decoder is used in the followingcases:• operand override prefix (66H)preceding an instruction withimmediate data• address override prefix (67H) precedingan instruction with a modr/m in real, bigreal, 16-bit protected or 32-bitprotected modesTo avoid instruction length decoding stalls,generate code using imm8 or imm32values instead of imm16 values.
If youmust use an imm16 value, store the valuein a register using “mov reg, imm32” anduse the register format of the instruction.88H00HBR_INST_EXECBranchinstructionsexecutedThis event counts all executed branches(not necessarily retired). This includes onlyinstructions and not micro-op branches.Frequent branching is not necessarily amajor performance issue. Howeverfrequent branch mispredictions may be aproblem.89H00HBR_MISSP_EXECMispredictedbranchinstructionsexecuted8AH00HBR_BAC_MISSP_EXECBranchThis event counts the number of branchinstructionsinstructions that were mispredicted atmispredicted at decoding.decodingA-26 Vol. 3This event counts the number ofmispredicted branch instructions thatwere executed.PERFORMANCE-MONITORING EVENTSTable A-3.
Non-Architectural Performance Eventsin Processors Based on Intel Core Microarchitecture (Contd.)EventNumUmaskValueEvent NameDefinitionDescription andComment8BH00HBR_CND_EXECConditionalbranchinstructionsexecuted.This event counts the number ofconditional branch instructions executed,but not necessarily retired.8CH00HBR_CND_MISSP_EXECMispredictedconditionalbranchinstructionsexecutedThis event counts the number ofmispredicted conditional branchinstructions that were executed.8DH00HBR_IND_EXECIndirect branchinstructionsexecutedThis event counts the number of indirectbranch instructions that were executed.8EH00HBR_IND_MISSP_EXECMispredictedindirect branchinstructionsexecutedThis event counts the number ofmispredicted indirect branch instructionsthat were executed.8FH00HBR_RET_EXECRETinstructionsexecutedThis event counts the number of RETinstructions that were executed.90H00HBR_RET_MISSP_EXECMispredictedRETinstructionsexecutedThis event counts the number ofmispredicted RET instructions that wereexecuted.91H00HBR_RET_BAC_MISSP_EXECRETThis event counts the number of RETinstructionsinstructions that were executed and wereexecutedmispredicted at decoding.mispredicted atdecoding92H00HBR_CALL_EXECCALLinstructionsexecutedThis event counts the number of CALLinstructions executed93H00HBR_CALL_MISSP_EXECMispredictedCALLinstructionsexecutedThis event counts the number ofmispredicted CALL instructions that wereexecuted.94H00HBR_IND_CALL_EXECIndirect CALLinstructionsexecutedThis event counts the number of indirectCALL instructions that were executed.Vol.
3 A-27PERFORMANCE-MONITORING EVENTSTable A-3. Non-Architectural Performance Eventsin Processors Based on Intel Core Microarchitecture (Contd.)EventNumUmaskValue97H00HDescription andCommentEvent NameDefinitionBR_TKN_BUBBLE_1BranchThe events BR_TKN_BUBBLE_1 andpredicted taken BR_TKN_BUBBLE_2 together count thewith bubble 1number of times a taken branch predictionincurred a one-cycle penalty. The penaltyincurs when:• Too many taken branches are placedtogether. To avoid this, unroll loops andadd a non-taken branch in the middle ofthe taken sequence.• The branch target is unaligned. To avoidthis, align the branch target.98H00HBR_TKN_BUBBLE_2The events BR_TKN_BUBBLE_1 andBranchpredicted taken BR_TKN_BUBBLE_2 together count thenumber of times a taken branch predictionwith bubble 2incurred a one-cycle penalty.
The penaltyincurs when:• Too many taken branches are placedtogether. To avoid this, unroll loops andadd a non-taken branch in the middle ofthe taken sequence.• The branch target is unaligned. To avoidthis, align the branch target.A0H00HRS_UOPS_DISPATCHEDMicro-opsdispatched forexecutionThis event counts the number of microops dispatched for execution. Up to sixmicro-ops can be dispatched in each cycle.A1H01HRS_UOPS_Cycles microDISPATCHED.PORT ops dispatched0for executionon port 0This event counts the number of cycles forwhich micro-ops dispatched for execution.Each cycle, at most one micro-op can bedispatched on the port. Issue Ports aredescribed in Intel® 64 and IA-32Architectures Optimization ReferenceManual.A1H02HRS_UOPS_Cycles microDISPATCHED.PORT ops dispatched1for executionon port 1This event counts the number of cycles forwhich micro-ops dispatched for execution.Each cycle, at most one micro-op can bedispatched on the port.A1H04HRS_UOPS_Cycles microDISPATCHED.PORT ops dispatched2for executionon port 2This event counts the number of cycles forwhich micro-ops dispatched for execution.Each cycle, at most one micro-op can bedispatched on the port.A-28 Vol.
3PERFORMANCE-MONITORING EVENTSTable A-3. Non-Architectural Performance Eventsin Processors Based on Intel Core Microarchitecture (Contd.)EventNumUmaskValueA1H08HRS_UOPS_Cycles microDISPATCHED.PORT ops dispatched3for executionon port 3This event counts the number of cycles forwhich micro-ops dispatched for execution.Each cycle, at most one micro-op can bedispatched on the port.A1H10HRS_UOPS_Cycles microDISPATCHED.PORT ops dispatched4for executionon port 4This event counts the number of cycles forwhich micro-ops dispatched for execution.Each cycle, at most one micro-op can bedispatched on the port.A1H20HRS_UOPS_Cycles microDISPATCHED.PORT ops dispatched5for executionon port 5This event counts the number of cycles forwhich micro-ops dispatched for execution.Each cycle, at most one micro-op can bedispatched on the port.AAH01HMACRO_INSTS.DECODEDInstructionsdecodedThis event counts the number ofinstructions decoded (but not necessarilyexecuted or retired).AAH08HMACRO_INSTS.CISC_DECODEDCISCInstructionsdecodedThis event counts the number of complexinstructions decoded.
Complex instructionsusually have more than four micro-ops.Only one complex instruction can bedecoded at a time.ABH01HESP.SYNCHESP registercontentsynchronizationThis event counts the number of timesthat the ESP register is explicitly used inthe address expression of a load or storeoperation, after it is implicitly used, forexample by a push or a pop instruction.Event NameDefinitionDescription andCommentESP synch micro-op uses resources fromthe rename pipe-stage and up toretirement.
The expected ratio of thisevent divided by the number of ESPimplicit changes is 0,2. If the ratio ishigher, consider rearranging your code toavoid ESP synchronization events.Vol. 3 A-29PERFORMANCE-MONITORING EVENTSTable A-3. Non-Architectural Performance Eventsin Processors Based on Intel Core Microarchitecture (Contd.)EventNumUmaskValueEvent NameDefinitionABH02HESP.ADDITIONSESP registerautomaticadditionsDescription andCommentThis event counts the number of ESPadditions performed automatically by thedecoder.
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