Volume 3B System Programming Guide_ Part 2 (794104), страница 72
Текст из файла (страница 72)
Architectural Performance EventsEventNum.Event MaskMnemonicUmaskValue3CHUnHalted Core Cycles 00HUnhalted core cycles3CHUnHalted ReferenceCyclesUnhalted reference cycles01HDescriptionCommentMeasures buscycle1Vol. 3 A-1PERFORMANCE-MONITORING EVENTSTable A-1. Architectural Performance EventsEventNum.Event MaskMnemonicUmaskValueDescriptionC0HInstruction Retired00HInstruction retired2EHLLC Reference4FHLL cache references2EHLLC Misses41HLL cache missesC4HBranch InstructionRetired00HBranch instruction retiredC5HBranch MissesRetired00HMispredicted Branch InstructionretiredCommentNOTES:1.
Implementation of this event in Intel Core 2 processor family, Intel Core Duo, and Intel Core Soloprocessors measures bus clocks.A.2PERFORMANCE MONITORING EVENTS FORINTEL® XEON® PROCESSOR 3000, 3200, 5100,5300 SERIES AND INTEL® CORE™2 DUOPROCESSORSProcessors based on Intel Core microarchitecture support architectural and nonarchitectural performance-monitoring events.Fixed-function performance counters are introduced first on processors based onIntel Core microarchitecture. Table A-2 lists pre-defined performance events that canbe counted using fixed-function performance counters.Table A-2. Fixed-Function Performance Counterand Pre-defined Performance EventsFixed-FunctionPerformanceCounterMSR_PERF_FIXED_CTR0A-2 Vol.
3AddressEvent MaskMnemonic309HInstr_Retired.AnyDescriptionThis event counts the number ofinstructions that retire execution. Forinstructions that consist of multiple microops, this event counts the retirement ofthe last micro-op of the instruction. Thecounter continue counting duringhardware interrupts, traps, and insideinterrupt handlersPERFORMANCE-MONITORING EVENTSTable A-2. Fixed-Function Performance Counterand Pre-defined Performance Events (Contd.)Fixed-FunctionPerformanceCounterMSR_PERF_FIXED_CTR1Address30AHEvent MaskMnemonicDescriptionCPU_CLK_UNHALT This event counts the number of coreED.COREcycles while the core is not in a halt state.The core enters the halt state when it isrunning the HLT instruction.
This event is acomponent in many key event ratios.The core frequency may change from timeto time due to transitions associated withEnhanced Intel SpeedStep Technology orTM2. For this reason this event may havea changing ratio with regards to time.When the core frequency is constant, thisevent can approximate elapsed time whilethe core was not in halt state.MSR_PERF_FIXED_CTR230BHCPU_CLK_UNHALT This event counts the number ofED.REFreference cycles when the core is not in ahalt state. The core enters the halt statewhen it is running the HLT instruction orthe MWAIT instruction.This event is not affected by corefrequency changes (e.g., P states, TM2transitions) but counts at the samefrequency as the time stamp counter.
Thisevent can approximate elapsed time whilethe core was not in halt state.This event has a constant ratio with theCPU_CLK_UNHALTED.BUS event.Table A-3 lists general-purpose non-architectural performance-monitoring eventssupported in processors based on Intel Core microarchitecture. For convenience,Table A-3 also includes architectural events and describes minor model-specificbehavior where applicable.
Software must use a general-purpose performancecounter to count events listed in Table A-3.Vol. 3 A-3PERFORMANCE-MONITORING EVENTSTable A-3. Non-Architectural Performance Eventsin Processors Based on Intel Core MicroarchitectureEventNumUmaskValueEvent NameDefinition03H02HLOAD_BLOCK.STALoads blockedby a precedingstore withunknownaddressDescription andCommentThis event indicates that loads are blockedby preceding stores. A load is blockedwhen there is a preceding store to anaddress that is not yet calculated.
Thenumber of events is greater or equal tothe number of load operations that wereblocked.If the load and the store are always todifferent addresses, check why thememory disambiguation mechanism is notworking. To avoid such blocks, increase thedistance between the store and thefollowing load so that the store address isknown at the time the load is dispatched.03H04HLOAD_BLOCK.STDLoads blockedby a precedingstore withunknown dataThis event indicates that loads are blockedby preceding stores.
A load is blockedwhen there is a preceding store to thesame address and the stored data value isnot yet known. The number of events isgreater or equal to the number of loadoperations that were blocked.To avoid such blocks, increase the distancebetween the store and the dependantload, so that the store data is known atthe time the load is dispatched.03H08HLOAD_BLOCK.OVERLAP_STORELoads thatpartiallyoverlap anearlier store, or4-Kbyte aliasedwith a previousstoreThis event indicates that loads are blockeddue to a variety of reasons. Some of thetriggers for this event are when a load isblocked by a preceding store, in one of thefollowing:• Some of the loaded byte locations arewritten by the preceding store andsome are not.• The load is from bytes written by thepreceding store, the store is aligned toits size and either:• The load’s data size is one or two bytesand it is not aligned to the store.• The load’s data size is of four or eightbytes and the load is misaligned.A-4 Vol.
3PERFORMANCE-MONITORING EVENTSTable A-3. Non-Architectural Performance Eventsin Processors Based on Intel Core Microarchitecture (Contd.)EventNumUmaskValueEvent NameDefinitionDescription andComment• The load is from bytes written by thepreceding store, the store is misalignedand the load is not aligned on thebeginning of the store.• The load is split over an eight byteboundary (excluding 16-byte loads).• The load and store have the sameoffset relative to the beginning ofdifferent 4-KByte pages. This case isalso called 4-KByte aliasing.In all these cases the load is blocked untilafter the blocking store retires and thestored data is committed to the cachehierarchy.03H10HLOAD_BLOCK.UNTIL_RETIRELoads blocked This event indicates that load operationsuntil retirement were blocked until retirement.
The numberof events is greater or equal to thenumber of load operations that wereblocked.This includes mainly uncacheable loadsand split loads (loads that cross the cacheline boundary) but may include other caseswhere loads are blocked until retirement.03H20HLOAD_BLOCK.L1DLoads blockedby the L1 datacacheThis event indicates that loads are blockeddue to one or more reasons. Sometriggers for this event are:• The number of L1 data cache missesexceeds the maximum number ofoutstanding misses supported by theprocessor. This includes missesgenerated as result of demand fetches,software prefetches or hardwareprefetches.• Cache line split loads.• Partial reads, such as reads to uncacheable memory, I/O instructions andmore.• A locked load operation is in progress.The number of events is greater orequal to the number of load operationsthat were blocked.Vol.
3 A-5PERFORMANCE-MONITORING EVENTSTable A-3. Non-Architectural Performance Eventsin Processors Based on Intel Core Microarchitecture (Contd.)EventNumUmaskValue04H01H04H02HDescription andCommentEvent NameDefinitionSB_DRAIN_CYCLESCycles whilestores areblocked due tostore bufferdrainThis event counts every cycle duringwhich the store buffer is draining.
Thisincludes:Cycles whilestore is waitingfor a precedingstore to begloballyobservedThis event counts the total duration, innumber of cycles, which stores are waitingfor a preceding stored cache line to beobserved by other cores.STORE_BLOCK.ORDER••••Serializing operations such as CPUIDSynchronizing operations such as XCHGInterrupt acknowledgmentOther conditions, such as cache flushingThis situation happens as a result of thestrong store ordering behavior, as definedin “Memory Ordering,” Chapter 7, Intel® 64and IA-32 Architectures SoftwareDeveloper’s Manual, Volume 3A.The stall may occur and be noticeable ifthere are many cases when a store eithermisses the L1 data cache or hits a cacheline in the Shared state.
If the storerequires a bus transaction to read thecache line then the stall ends when snoopresponse for the bus transaction arrives.04H08HSTORE_BLOCK.SNOOPA store isblocked due toa conflict withan external orinternal snoop.This event counts the number of cyclesthe store port was used for snooping theL1 data cache and a store was stalled bythe snoop. The store is typicallyresubmitted one cycle later.06H00HSEGMENT_REG_LOADSNumber ofsegmentregister loadsThis event counts the number of segmentregister load operations. Instructions thatload new values into segment registerscause a penalty.A-6 Vol. 3PERFORMANCE-MONITORING EVENTSTable A-3.
Non-Architectural Performance Eventsin Processors Based on Intel Core Microarchitecture (Contd.)EventNumUmaskValueEvent NameDefinitionDescription andCommentThis event indicates performance issues in16-bit code. If this event occursfrequently, it may be useful to calculatethe number of instructions retired persegment register load. If the resultingcalculation is low (on average a smallnumber of instructions are executedbetween segment register loads), then thecode’s segment register usage should beoptimized.As a result of branch misprediction, thisevent is speculative and may includesegment register loads that do notactually occur.
However, most segmentregister loads are internally serialized andsuch speculative effects are minimized.07H00HSSE_PRE_EXEC.NTAStreaming SIMDExtensions(SSE) PrefetchNTAinstructionsexecutedThis event counts the number of times theSSE instruction prefetchNTA is executed.This instruction prefetches the data to theL1 data cache.07H01HSSE_PRE_EXEC.L1Streaming SIMDExtensions(SSE)PrefetchT0instructionsexecutedThis event counts the number of times theSSE instruction prefetchT0 is executed.This instruction prefetches the data to theL1 data cache and L2 cache.07H02HSSE_PRE_EXEC.L2StreamingSIMDExtensions(SSE)PrefetchT1 andPrefetchT2instructionsexecutedThis event counts the number of times theSSE instructions prefetchT1 andprefetchT2 are executed.
Theseinstructions prefetch the data to the L2cache.Vol. 3 A-7PERFORMANCE-MONITORING EVENTSTable A-3. Non-Architectural Performance Eventsin Processors Based on Intel Core Microarchitecture (Contd.)EventNumUmaskValue07H08HDescription andCommentEvent NameDefinition03HSSE_PRE_EXEC.STORESStreaming SIMD This event counts the number of timesExtensionsSSE non-temporal store instructions are(SSE) Weaklyexecuted.ordered storeinstructionsexecuted01HDTLB_MISSES.ANYMemoryaccesses thatmissed theDTLBThis event counts the number of DataTable Lookaside Buffer (DTLB) misses. Thecount includes misses detected as a resultof speculative accesses.Typically a high count for this eventindicates that the code accesses a largenumber of data pages.08H02HDTLB_MISSES.MISS_LDDTLB missesdue to loadoperationsThis event counts the number of DataTable Lookaside Buffer (DTLB) misses dueto load operations.This count includes misses detected as aresult of speculative accesses.08H04HDTLB_MISSES.L0_MISS_LDL0 DTLB misses This event counts the number of level 0due to loadData Table Lookaside Buffer (DTLB0)operationsmisses due to load operations.This count includes misses detected as aresult of speculative accesses.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
