Volume 3B System Programming Guide_ Part 2 (794104), страница 69
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A VMM with hostcontrol of NMI and external interrupts can use the event-injection facility toforward virtual interruptions to various guest virtual machines.27-2 Vol. 3HANDLING BOUNDARY CONDITIONS IN A VIRTUAL MACHINE MONITOR•Interrupt-window Exiting. The interrupt-window exiting control bit in theVM-execution controls (Section 20.6.2) causes VM exits when guest RFLAGS.IF is1 and no other conditions block external interrupts. If the control is 1, a VM exitoccurs at the beginning of any instruction at which RFLAGS.IF = 1 and on whichthe interruptibility state of the guest would allow delivery of an interrupt. Forexample: when the guest executes an STI instruction, RFLAGS = 1, and if at thecompletion of next instruction the interruptibility state masking due to STI isremoved; a VM exit occurs if interrupt-window exiting control is 1. The interruptwindow exiting feature allows a VMM to queue a virtual interrupt to the guestwhen the guest is not in an interruptible state.
The VMM can set the interruptwindow exiting control for the guest and depend on a VM exit to know when theguest becomes interruptible (and, therefore, when it can inject a virtualinterrupt). The VMM can detect such VM exits by checking for the basic exitreason ‘interrupt-window’ (value = 7). Without interrupt-window exiting support,the VMM will need to poll and check the interruptibility state of the guest todeliver virtual interrupts.•NMI-window Exiting.
If the “virtual NMIs” VM-execution is set, the processortracks virtual-NMI blocking. The NMI-window exiting control bit in VM-executioncontrols (Section 20.6.2) causes VM exits when there is no virtual-NMI blocking.For example, after execution of the IRET instruction, a VM exit occurs if NMIwindow exiting control is 1. The NMI-window exiting feature allows a VMM toqueue a virtual NMI to a guest when the guest is not ready to receive NMIs. TheVMM can set the NMI-window exiting control for the guest and depend on aVM exit to know when the guest becomes ready for NMIs (and, therefore, when itcan inject a virtual NMI). The VMM can detect such VM exits by checking for thebasic exit reason ‘NMI window’ (value = 8). Without NMI-window exiting support,the VMM will need to poll and check the interruptibility state of the guest todeliver virtual NMIs.•VM-Exit Information.
The VM-exit information fields provide details onVM exits due to exceptions and interrupts. This information is provided throughthe exit-qualification, VM-exit-interruption-information, instruction-length andinterruption-error-code fields. Also, for VM exits that occur in the course ofvectoring through the guest-IDT, information about the event that was beingvectored through the guest-IDT is provided in the IDT-vectoring-information andIDT-vectoring-error-code fields. These information fields allow the VMM toidentify the exception cause and to handle it properly.27.3EXTERNAL INTERRUPT VIRTUALIZATIONVMX operation allows both host and guest control of external interrupts. While guestcontrol of external interrupts might be suitable for partitioned usages (different CPUcores/threads and I/O devices partitioned to independent virtual machines), mostVMMs built upon VMX are expected to utilize host control of external interrupts.
Therest of this section describes a general host-controlled interrupt virtualization architecture for standard PC platforms through the use of VMX supported features.Vol. 3 27-3HANDLING BOUNDARY CONDITIONS IN A VIRTUAL MACHINE MONITORWith host control of external interrupts, the VMM (or the host OS in a hosted VMMmodel) manages the physical interrupt controllers in the platform and the interruptsgenerated through them. The VMM exposes software-emulated virtual interruptcontroller devices (such as PIC and APIC) to each guest virtual machine instance.27.3.1Virtualization of Interrupt Vector SpaceThe Intel 64 and IA-32 architectures use 8-bit vectors of which 244 (20H - FFH) areavailable for external interrupts.
Vectors are used to select the appropriate entry inthe interrupt descriptor table (IDT). VMX operation allows each guest to control itsown IDT. Host vectors refer to vectors delivered by the platform to the processorduring the interrupt acknowledgement cycle. Guest vectors refer to vectorsprogrammed by a guest to select an entry in its guest IDT. Depending on the I/Oresource management models supported by the VMM design, the guest vector spacemay or may not overlap with the underlying host vector space.•Interrupts from virtual devices: Guest vector numbers for virtual interruptsdelivered to guests on behalf of emulated virtual devices have no direct relationto the host vector numbers of interrupts from physical devices on which they areemulated.
A guest-vector assigned for a virtual device by the guest operatingenvironment is saved by the VMM and utilized when injecting virtual interrupts onbehalf of the virtual device.•Interrupts from assigned physical devices: Hardware support for I/O deviceassignment allows physical I/O devices in the host platform to be assigned(direct-mapped) to VMs. Guest vectors for interrupts from direct-mappedphysical devices take up equivalent space from the host vector space, andrequire the VMM to perform host-vector to guest-vector mapping for interrupts.Figure 27-1 illustrates the functional relationship between host external interruptsand guest virtual external interrupts.
Device A is owned by the host and generatesexternal interrupts with host vector X. The host IDT is set up such that the interruptservice routine (ISR) for device driver A is hooked to host vector X as normal. VMMemulates (over device A) virtual device C in software which generates virtual interrupts to the VM with guest expected vector P. Device B is assigned to a VM and generates external interrupts with host vector Y. The host IDT is programmed to hook theVMM interrupt service routine (ISR) for assigned devices for vector Y, and the VMMhandler injects virtual interrupt with guest vector Q to the VM.
The guest operatingsystem programs the guest to hook appropriate guest driver’s ISR to vectors Pand Q.27-4 Vol. 3HANDLING BOUNDARY CONDITIONS IN A VIRTUAL MACHINE MONITORVMDevice Driver CGuest IDTDevice Driver BGuestVector PGuestVector QGuest IDTRVirtual InterruptVirtual InterruptVirtual Device CEmulationHost IDTMonitor HandlerPlatform InterruptVector YHostVirtual Machine Monitor (VMM)HostHost IDTRVector XDevice Driver APlatform InterruptHardwareDevice ADevice BOM19041Figure 27-1.
Host External Interrupts and Guest Virtual Interrupts27.3.2Control of Platform InterruptsTo meet the interrupt virtualization requirements, the VMM needs to take ownershipof the physical interrupts and the various interrupt controllers in the platform. VMMcontrol of physical interrupts may be enabled through the host-control settings of the“external-interrupt exiting” VM-execution control. To take ownership of the platforminterrupt controllers, the VMM needs to expose the virtual interrupt controller devicesto the virtual machines and restrict guest access to the platform interrupt controllers.Intel 64 and IA-32 platforms can support three types of external interrupt controlmechanisms: Programmable Interrupt Controllers (PIC), Advanced ProgrammableVol.
3 27-5HANDLING BOUNDARY CONDITIONS IN A VIRTUAL MACHINE MONITORInterrupt Controllers (APIC), and Message Signaled Interrupts (MSI). The followingsections provide information on the virtualization of each of these mechanisms.27.3.2.1PIC VirtualizationTypical PIC-enabled platform implementations support dual 8259 interrupt controllers cascaded as master and slave controllers.
They supporting up to 15 possibleinterrupt inputs. The 8259 controllers are programmed through initializationcommand words (ICWx) and operation command words (OCWx) accessed throughspecific I/O ports. The various interrupt line states are captured in the PIC throughinterrupt requests, interrupt service routines and interrupt mask registers.Guest access to the PIC I/O ports can be restricted by activating I/O bitmaps in theguest controlling-VMCS (activate-I/O-bitmap bit in VM-execution control field setto 1) and pointing the I/O-bitmap physical addresses to valid bitmap regions.
Bitscorresponding to the PIC I/O ports can be cleared to cause a VM exit on guest accessto these ports.If the VMM is not supporting direct access to any I/O ports from a guest, it can set theunconditional-I/O-exiting in the VM-execution control field instead of activating I/Obitmaps. The exit-reason field in VM-exit information allows identification of VM exitsdue to I/O access and can provide an exit-qualification to identify details about theguest I/O operation that caused the VM exit.The VMM PIC virtualization needs to emulate the platform PIC functionality includinginterrupt priority, mask, request and service states, and specific guest programmedmodes of PIC operation.27.3.2.2xAPIC VirtualizationMost modern Intel 64 and IA-32 platforms include support for an APIC.
While thestandard PIC is intended for use on uniprocessor systems, APIC can be used in eitheruniprocessor or multi-processor systems.APIC based interrupt control consists of two physical components: the interruptacceptance unit (Local APIC) which is integrated with the processor, and the interruptdelivery unit (I/O APIC) which is part of the I/O subsystem. APIC virtualizationinvolves protecting the platform’s local and I/O APICs and emulating them for theguest.27.3.2.3Local APIC VirtualizationThe local APIC is responsible for the local interrupt sources, interrupt acceptance,dispensing interrupts to the logical processor, and generating inter-processor interrupts. Software interacts with the local APIC by reading and writing its memorymapped registers residing within a 4-KByte uncached memory region with baseaddress stored in the IA32_APIC_BASE MSR.
Since the local APIC registers arememory-mapped, the VMM can utilize memory virtualization techniques (such as27-6 Vol. 3HANDLING BOUNDARY CONDITIONS IN A VIRTUAL MACHINE MONITORpage-table virtualization) to trap guest accesses to the page frame hosting thevirtual local APIC registers.Local APIC virtualization in the VMM needs to emulate the various local APIC operations and registers, such as: APIC identification/format registers, the local vectortable (LVT), the interrupt command register (ICR), interrupt capture registers (TMR,IRR and ISR), task and processor priority registers (TPR, PPR), the EOI register andthe APIC-timer register. Since local APICs are designed to operate with non-specificEOI, local APIC emulation also needs to emulate broadcast of EOI to the guest’svirtual I/O APICs for level triggered virtual interrupts.A local APIC allows interrupt masking at two levels: (1) mask bit in the local vectortable entry for local interrupts and (2) raising processor priority through the TPRregisters for masking lower priority external interrupts.
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