Volume 3B System Programming Guide_ Part 2 (794104), страница 74
Текст из файла (страница 74)
This includes L1 data cachereads, writes, and locked accesses, L1 dataprefetch requests, and instruction fetches.This is an architectural performance event.2EH4FHL2_RQSTS.SELF.DEMAND.MESIL2 cachedemandrequests fromthis coreThis event counts all completed L2 cachedemand requests from this core. Thisincludes L1 data cache reads, writes, andlocked accesses, L1 data prefetchrequests, and instruction fetches.This is an architectural performance event.30HSeeTable18-7,Table18-9,andTable18-10L2_REJECT_BUSQ.( Rejected L2This event indicates that a pending L2Core, Prefetch,cache requests cache request that requires a busCache Line State)transaction is delayed from moving to thebus queue. Some of the reasons for thisevent are:• The bus queue is full.• The bus queue already holds an entryfor a cache line in the same set.The number of events is greater or equalto the number of requests that wererejected.• for this core or both cores.• due to demand requests and L2hardware prefetch requests together,or separately.• of accesses to cache lines at differentMESI states.32HSeeTable18-7L2_NO_REQ.(Core) Cycles no L2This event counts the number of cyclescache requests that no L2 cache requests were pendingare pendingfrom a core.
When using the BOTH_COREmodifier, the event counts only if none ofthe cores have a pending request. Theevent counts also when one core is haltedand the other is not halted.The event can count occurrences for thiscore or both cores.A-14 Vol. 3PERFORMANCE-MONITORING EVENTSTable A-3. Non-Architectural Performance Eventsin Processors Based on Intel Core Microarchitecture (Contd.)EventNumUmaskValueEvent NameDefinitionDescription andComment3AH00HEIST_TRANSNumber ofEnhanced IntelSpeedStepTechnology(EIST)transitionsThis event counts the number oftransitions that include a frequencychange, either with or without voltagechange.
This includes Enhanced IntelSpeedStep Technology (EIST) and TM2transitions.The event is incremented only while thecounting core is in C0 state. Sincetransitions to higher-numbered CxE statesand TM2 transitions include a frequencychange or voltage transition, the event isincremented accordingly.3BHC0HTHERMAL_TRIPNumber ofthermal tripsThis event counts the number of thermaltrips. A thermal trip occurs whenever theprocessor temperature exceeds thethermal trip threshold temperature.Following a thermal trip, the processorautomatically reduces frequency andvoltage.
The processor checks thetemperature every millisecond and returnsto normal when the temperature fallsbelow the thermal trip thresholdtemperature.3CH00HCPU_CLK_UNHALTED.CORE_PCore cycleswhen core isnot haltedThis event counts the number of corecycles while the core is not in a halt state.The core enters the halt state when it isrunning the HLT instruction.
This event is acomponent in many key event ratios.The core frequency may change due totransitions associated with Enhanced IntelSpeedStep Technology or TM2. For thisreason, this event may have a changingratio in regard to time.When the core frequency is constant, thisevent can give approximate elapsed timewhile the core not in halt state.This is an architectural performance event.Vol.
3 A-15PERFORMANCE-MONITORING EVENTSTable A-3. Non-Architectural Performance Eventsin Processors Based on Intel Core Microarchitecture (Contd.)EventNumUmaskValue3CH01HEvent NameDefinitionCPU_CLK_UNHALTED.BUSBus cycleswhen core isnot haltedDescription andCommentThis event counts the number of buscycles while the core is not in the haltstate.
This event can give a measurementof the elapsed time while the core was notin the halt state. The core enters the haltstate when it is running the HLTinstruction.The event also has a constant ratio withCPU_CLK_UNHALTED.REF event, which isthe maximum bus to processor frequencyratio.Non-halted bus cycles are a component inmany key event ratios.3CH02HCPU_CLK_UNHALTED.NO_OTHERBus cycleswhen core isactive and theother is haltedThis event counts the number of buscycles during which the core remains nonhalted and the other core on the processoris halted.This event can be used to determine theamount of parallelism exploited by anapplication or a system. Divide this eventcount by the bus frequency to determinethe amount of time that only one core wasin use.40HSeeTable18-10L1D_CACHE_LD.(Cache Line State)L1 cacheabledata readsThis event counts the number of datareads from cacheable memory.
Lockedreads are not counted.41HSeeTable18-10L1D_CACHE_ST.(Cache Line State)L1 cacheabledata writesThis event counts the number of datawrites to cacheable memory. Lockedwrites are not counted.42HSeeTable18-10L1D_CACHE_LOCK.(Cache LineState)L1 datacacheablelocked readsThis event counts the number of lockeddata reads from cacheable memory.A-16 Vol.
3PERFORMANCE-MONITORING EVENTSTable A-3. Non-Architectural Performance Eventsin Processors Based on Intel Core Microarchitecture (Contd.)EventNumUmaskValue42H10H43H10HDescription andCommentEvent NameDefinitionL1D_CACHE_LOCK_DURATIONDuration of L1data cacheablelockedoperationThis event counts the number of cyclesduring which any cache line is locked byany locking instruction.All referencesto the L1 datacacheThis event counts all references to the L1data cache, including all loads and storeswith any memory types.L1D_ALL_REFLocking happens at retirement andtherefore the event does not occur forinstructions that are speculativelyexecuted.
Locking duration is shorter thanlocked instruction execution duration.The event counts memory accesses onlywhen they are actually performed. Forexample, a load blocked by unknown storeaddress and later performed is onlycounted once.The event includes non-cacheableaccesses, such as I/O accesses.43H02HL1D_ALL_CACHE_REFL1 Datacacheablereads andwritesThis event counts the number of datareads and writes from cacheable memory,including locked operations.This event is a sum of:• L1D_CACHE_LD.MESI• L1D_CACHE_ST.MESI• L1D_CACHE_LOCK.MESI45H0FHL1D_REPLCache linesThis event counts the number of linesallocated in the brought into the L1 data cache.L1 data cache46H00HL1D_M_REPLModified cachelines allocatedin the L1 datacacheThis event counts the number of modifiedlines brought into the L1 data cache.47H00HL1D_M_EVICTModified cachelines evictedfrom the L1data cacheThis event counts the number of modifiedlines evicted from the L1 data cache,whether due to replacement or by snoopHITM intervention.Vol.
3 A-17PERFORMANCE-MONITORING EVENTSTable A-3. Non-Architectural Performance Eventsin Processors Based on Intel Core Microarchitecture (Contd.)EventNumUmaskValue48H00HEvent NameDefinitionL1D_PEND_MISSTotal number ofoutstanding L1data cachemisses at anycycleDescription andCommentThis event counts the number ofoutstanding L1 data cache misses at anycycle. An L1 data cache miss isoutstanding from the cycle on which themiss is determined until the first chunk ofdata is available. This event counts:• all cacheable demand requests• L1 data cache hardware prefetchrequests• requests to write through memory• requests to write combine memoryUncacheable requests are not counted.The count of this event divided by thenumber of L1 data cache misses,L1D_REPL, is the average duration in corecycles of an L1 data cache miss.49H01HL1D_SPLIT.LOADSCache line splitloads from theL1 data cacheThis event counts the number of loadoperations that span two cache lines.
Suchload operations are also called split loads.Split load operations are executed atretirement.49H02HL1D_SPLIT.STORESCache line splitstores to theL1 data cacheThis event counts the number of storeoperations that span two cache lines.4BH00HSSE_PRE_MISS.NTAStreaming SIMDExtensions(SSE) PrefetchNTAinstructionsmissing allcache levelsThis event counts the number of times theSSE instructions prefetchNTA wereexecuted and missed all cache levels.Streaming SIMDExtensions(SSE)PrefetchT0instructionsmissing allcache levelsThis event counts the number of times theSSE instructions prefetchT0 wereexecuted and missed all cache levels.4BH01HA-18 Vol.
3SSE_PRE_MISS.L1Due to speculation an executed instructionmight not retire. This instructionprefetches the data to the L1 data cache.Due to speculation executed instructionmight not retire. The prefetchT0instruction prefetches data to the L2cache and L1 data cache.PERFORMANCE-MONITORING EVENTSTable A-3. Non-Architectural Performance Eventsin Processors Based on Intel Core Microarchitecture (Contd.)EventNumUmaskValue4BH02HDescription andCommentEvent NameDefinitionSSE_PRE_MISS.L2Streaming SIMDExtensions(SSE)PrefetchT1 andPrefetchT2instructionsmissing allcache levelsThis event counts the number of times theSSE instructions prefetchT1 andprefetchT2 were executed and missed allcache levels.Due to speculation, an executedinstruction might not retire.
TheprefetchT1 and PrefetchNT2 instructionsprefetch data to the L2 cache.4CH00HLOAD_HIT_PRELoadoperationsconflicting witha softwareprefetch to thesame addressThis event counts load operations sent tothe L1 data cache while a previousStreaming SIMD Extensions (SSE) prefetchinstruction to the same cache line hasstarted prefetching but has not yetfinished.4EH10HL1D_PREFETCH.REQUESTSL1 data cacheprefetchrequestsThis event counts the number of times theL1 data cache requested to prefetch adata cache line.
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