Volume 3B System Programming Guide_ Part 2 (794104), страница 96
Текст из файла (страница 96)
MSRs in the Pentium 4 and Intel Xeon Processors (Contd.)RegisterAddressHexDec191H401Register NameFields and FlagsIA32_MCG_R9ModelAvailabilityShared/Unique10, 1, 2,3, 4, 6Unique402IA32_MCG_R10Registers R8-15 (and theassociated state-save MSRs) existonly in Intel 64 processors. Theseregisters contain valid informationonly when the processor isoperating in 64-bit mode at thetime of the error.0, 1, 2,3, 4, 6Unique403IA32_MCG_R11Registers R8-15 (and theassociated state-save MSRs) existonly in Intel 64 processors.
Theseregisters contain valid informationonly when the processor isoperating in 64-bit mode at thetime of the error.0, 1, 2,3, 4, 6Unique404IA32_MCG_R12Machine Check R11.See Section 14.3.2.5, “IA32_MCGExtended Machine Check StateMSRs.”63-0194HMachine Check R10.See Section 14.3.2.5, “IA32_MCGExtended Machine Check StateMSRs.”63-0193HMachine Check R9D/R9.See Section 14.3.2.5, “IA32_MCGExtended Machine Check StateMSRs.”63-0192HBit DescriptionRegisters R8-15 (and theassociated state-save MSRs) existonly in Intel 64 processors.
Theseregisters contain valid informationonly when the processor isoperating in 64-bit mode at thetime of the error.0, 1, 2,3, 4, 6UniqueMachine Check R12.See Section 14.3.2.5, “IA32_MCGExtended Machine Check StateMSRs.”Vol. 3 B-39MODEL-SPECIFIC REGISTERS (MSRS)Table B-2. MSRs in the Pentium 4 and Intel Xeon Processors (Contd.)RegisterAddressHexRegister NameFields and FlagsDecModelAvailabilityShared/Unique163-0195H405IA32_MCG_R13Registers R8-15 (and theassociated state-save MSRs) existonly in Intel 64 processors. Theseregisters contain valid informationonly when the processor isoperating in 64-bit mode at thetime of the error.0, 1, 2,3, 4, 6Unique406IA32_MCG_R14Registers R8-15 (and theassociated state-save MSRs) existonly in Intel 64 processors. Theseregisters contain valid informationonly when the processor isoperating in 64-bit mode at thetime of the error.0, 1, 2,3, 4, 6UniqueB-40 Vol. 3407IA32_MCG_R15Machine Check R14.See Section 14.3.2.5, “IA32_MCGExtended Machine Check StateMSRs.”63-0197HMachine Check R13.See Section 14.3.2.5, “IA32_MCGExtended Machine Check StateMSRs.”63-0196HBit DescriptionRegisters R8-15 (and theassociated state-save MSRs) existonly in Intel 64 processors.
Theseregisters contain valid informationonly when the processor isoperating in 64-bit mode at thetime of the error.0, 1, 2,3, 4, 6UniqueMachine Check R15.See Section 14.3.2.5, “IA32_MCGExtended Machine Check StateMSRs.”MODEL-SPECIFIC REGISTERS (MSRS)Table B-2. MSRs in the Pentium 4 and Intel Xeon Processors (Contd.)RegisterAddressHexRegister NameFields and FlagsDecModelAvailabilityShared/Unique163-0198H199H19AH408409410IA32_PERF_STATUSBit DescriptionRegisters R8-15 (and theassociated state-save MSRs) existonly in Intel 64 processors. Theseregisters contain valid informationonly when the processor isoperating in 64-bit mode at thetime of the error.3, 4, 6UniqueSee Section 13.1, “Enhanced IntelSpeedstep® Technology.”15:0Current Performance StateValue. (RO)63:16ReservedIA32_PERF_CTL3, 4, 6UniqueSee Section 13.1, “Enhanced IntelSpeedstep® Technology.”15:0Target Performance State Value.(R/W)63:16ReservedIA32_CLOCK_MODULATION0, 1, 2,3, 4, 6UniqueThermal Monitor Control.
(R/W)Enables and disables on-demandclock modulation and allowsselection of the on-demand clockmodulation duty cycle.See Section 13.5.3, “SoftwareControlled Clock Modulation.”19BH411IA32_THERM_INTERRUPT0, 1, 2,3, 4, 6UniqueThermal Interrupt Control. (R/W)Enables and disables thegeneration of an interrupt ontemperature transitions detectedwith the processor’s thermalsensor and thermal monitor.See Section 13.5.2, “ThermalMonitor.”Vol. 3 B-41MODEL-SPECIFIC REGISTERS (MSRS)Table B-2.
MSRs in the Pentium 4 and Intel Xeon Processors (Contd.)RegisterAddressHexDec19CH412Register NameFields and FlagsModelAvailabilityShared/Unique1IA32_THERM_STATUS0, 1, 2,3, 4, 6SharedBit DescriptionThermal Monitor Status. (R/W)Contains status information aboutthe processor’s thermal sensorand automatic thermal monitoringfacilities.See Section 13.5.2, “ThermalMonitor.”19DH1A0H413416IMSR_THERM2_CTLIA32_MISC_ENABLEThermal Monitor 2 Control.3SharedFor Family F, Model 3 processors:When read, specifies the value ofthe target TM2 transition lastwritten.
When set, it sets the nexttarget value for TM2 transition.4, 6SharedFor Family F, Model 4 and Model 6processors: When read, specifiesthe value of the target TM2transition last written. Writes maycause #GP exceptions.0, 1, 2,3, 4, 6SharedEnable Miscellaneous ProcessorFeatures. (R/W)Allows a variety of processorfunctions to be enabled anddisabled.0Fast-Strings Enable.When set, the fast-strings featureon the Pentium 4 processor isenabled (default); when clear, faststrings are disabled.1B-42 Vol. 3Reserved.MODEL-SPECIFIC REGISTERS (MSRS)Table B-2. MSRs in the Pentium 4 and Intel Xeon Processors (Contd.)RegisterAddressHexRegister NameFields and FlagsDec2ModelAvailabilityShared/Unique1Bit Descriptionx87 FPU Fopcode CompatibilityMode Enable.When set, fopcode compatibilitymode is enabled; when clear(default), mode is disabled.See “Fopcode Compatibility Mode“in Chapter 8 of the Intel® 64 andIA-32 Architectures SoftwareDeveloper’s Manual, Volume 1.3Thermal Monitor 1 Enable.When set, clock modulationcontrolled by the processor’sinternal thermal sensor is enabled;when clear (default), automaticclock modulation is disabled.See Section 13.5.2, “ThermalMonitor.”4Split-Lock Disable.This debug feature is specific tothe Pentium 4 processor.When set, the bit causes an #ACexception to be issued instead of asplit-lock cycle.
Operating systemsthat set this bit must align systemstructures to avoid split-lockscenarios.When the bit is clear (default),normal split-locks are issued to thebus.5Reserved.6Third-Level Cache Disable. (R/W)When set, the third-level cache isdisabled; when clear (default) thethird-level cache is enabled. Thisflag is reserved for processorsthat do not have a third-levelcache.Vol.
3 B-43MODEL-SPECIFIC REGISTERS (MSRS)Table B-2. MSRs in the Pentium 4 and Intel Xeon Processors (Contd.)RegisterAddressHexRegister NameFields and FlagsDecModelAvailabilityShared/Unique1Bit DescriptionNote that the bit controls only thethird-level cache; and only ifoverall caching is enabled throughthe CD flag of control register CR0,the page-level cache controls,and/or the MTRRs.See Section 10.5.4, “Disabling andEnabling the L3 Cache.”7Performance MonitoringAvailable.
(R)When set, performance monitoringis enabled; when clear,performance monitoring isdisabled.8Suppress Lock Enable.When set, assertion of LOCK onthe bus is suppressed during aSplit Lock access. When clear(default), LOCK is not suppressed.9Prefetch Queue Disable.When set, disables the prefetchqueue.
When clear (default),enables the prefetch queue.10FERR# Interrupt ReportingEnable. (R/W)When set, interrupt reportingthrough the FERR# pin is enabled;when clear, this interruptreporting function is disabled.B-44 Vol. 3MODEL-SPECIFIC REGISTERS (MSRS)Table B-2. MSRs in the Pentium 4 and Intel Xeon Processors (Contd.)RegisterAddressHexRegister NameFields and FlagsDecModelAvailabilityShared/Unique1Bit DescriptionWhen this flag is set and theprocessor is in the stop-clock state(STPCLK# is asserted), assertingthe FERR# pin signals to theprocessor that an interrupt (suchas, INIT#, BINIT#, INTR, NMI, SMI#,or RESET#) is pending and thatthe processor should return tonormal operation to handle theinterrupt.This flag does not affect thenormal operation of the FERR# pin(to indicate an unmasked floatingpoint error) when the STPCLK#pin is not asserted.11Branch Trace StorageUnavailable (BTS_UNAVILABLE).(R)When set, the processor does notsupport branch trace storage(BTS); when clear, BTS issupported.12Precise Event Based SamplingUnavailable(PEBS_UNAVILABLE).
(R)When set, the processor does notsupport precise event-basedsampling (PEBS); when clear, PEBSis supported.133TM2 Enable. (R/W)When this bit is set (1) and thethermal sensor indicates that thedie temperature is at the predetermined threshold, theThermal Monitor 2 mechanism isengaged. TM2 will reduce the busto core ratio and voltage accordingto the value last written toMSR_THERM2_CTL bits 15:0.Vol. 3 B-45MODEL-SPECIFIC REGISTERS (MSRS)Table B-2.
MSRs in the Pentium 4 and Intel Xeon Processors (Contd.)RegisterAddressHexRegister NameFields and FlagsDecModelAvailabilityShared/Unique1Bit DescriptionWhen this bit is clear (0, default),the processor does not change theVID signals or the bus to core ratiowhen the processor enters athermal managed state.If the TM2 feature flag (ECX[8]) isnot set to 1 after executing CPUIDwith EAX = 1, then this feature isnot supported and BIOS must notalter the contents of this bitlocation. The processor isoperating out of spec if both thisbit and the TM1 bit are set todisabled states.17:1418Reserved.3, 4, 6ENABLE MONITOR FSM. (R/W)When set (default), the MONITORand MWAIT instructions areenabled.
When clear, theseinstructions are disabled andattempting to execute themresults in an invalid opcodeexception.CPUID.1:EAX.MONITOR[bit 3]indicates the setting of the EnableMonitor FSM bit. IfCPUID.1:ECX.SSE3[bit 0] is not set,then the operating system mustnot attempt to alter the setting ofthe Enable Monitor FSM bit. BIOSshould leave this bit in the defaultstate.B-46 Vol.
3MODEL-SPECIFIC REGISTERS (MSRS)Table B-2. MSRs in the Pentium 4 and Intel Xeon Processors (Contd.)RegisterAddressHexRegister NameFields and FlagsDecModelAvailability19Shared/Unique1Bit DescriptionAdjacent Cache Line PrefetchDisable. (R/W)When set to 1, the processorfetches the cache line of the 128byte sector containing currentlyrequired data. When set to 0, theprocessor fetches both cache linesin the sector.Single processor platforms shouldnot set this bit. Server platformsshould set or clear this bit basedon platform performanceobserved in validation and testing.BIOS may contain a setup optionthat controls the setting of this bit.21:2022Reserved.3, 4, 6Limit CPUID MAXVAL. (R/W)When set to 1, CPUID withEAX = 0 returns a maximum valuein EAX[7:0] of 3. When set to a 0(default), CPUID with EAX = 0returns the number correspondingto the maximum standard functionsupported.Some older OS's cannot handle aMAXVAL greater than 3. BIOSshould contain a setup questionthat allows the user to specifysuch an OS is installed.
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