Volume 3B System Programming Guide_ Part 2 (794104), страница 99
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3MODEL-SPECIFIC REGISTERS (MSRS)Table B-2. MSRs in the Pentium 4 and Intel Xeon Processors (Contd.)RegisterAddressHexRegister NameFields and FlagsDecModelAvailabilityShared/Unique1Bit DescriptionWhen not implemented in theprocessor, all reads and writes tothis MSR will cause a generalprotection exception.480H1152IA32_VMX_BASIC3, 4, 6UniqueReporting Register of Basic VMXCapabilities. (R/O)See Appendix G.1, “Basic VMXInformation”(If CPUID.01H:ECX.[bit 9])481H1153IA32_VMX_PINBASED_CTLS3, 4, 6UniqueCapability Reporting Register ofPin-based VM-executionControls. (R/O)See Appendix G.2, “VM-ExecutionControls”(If CPUID.01H:ECX.[bit 9])482H1154IA32_VMX_PROCBASED_CTLS3, 4, 6UniqueCapability Reporting Register ofPrimary Processor-basedVM-execution Controls.
(R/O)See Appendix G.2, “VM-ExecutionControls”(If CPUID.01H:ECX.[bit 9])483H1155IA32_VMX_EXIT_CTLS3, 4, 6UniqueCapability Reporting Register ofVM-exit Controls. (R/O)See Appendix G.3, “VM-ExitControls”(If CPUID.01H:ECX.[bit 9])484H1156IA32_VMX_ENTRY_CTLS3, 4, 6UniqueCapability Reporting Register ofVM-entry Controls. (R/O)See Appendix G.4, “VM-EntryControls”(If CPUID.01H:ECX.[bit 9])Vol. 3 B-65MODEL-SPECIFIC REGISTERS (MSRS)Table B-2. MSRs in the Pentium 4 and Intel Xeon Processors (Contd.)RegisterAddressHexDec485H1157Register NameFields and FlagsIA32_VMX_MISCModelAvailabilityShared/Unique13, 4, 6UniqueBit DescriptionReporting Register ofMiscellaneous VMX Capabilities.(R/O)See Appendix G.5, “MiscellaneousData”(If CPUID.01H:ECX.[bit 9])486H1158IA32_VMX_CR0_FIXED03, 4, 6UniqueCapability Reporting Register ofCR0 Bits Fixed to 0.
(R/O)See Appendix G.6, “VMX-Fixed Bitsin CR0”(If CPUID.01H:ECX.[bit 9])487H1159IA32_VMX_CR0_FIXED13, 4, 6UniqueCapability Reporting Register ofCR0 Bits Fixed to 1. (R/O)See Appendix G.6, “VMX-Fixed Bitsin CR0”(If CPUID.01H:ECX.[bit 9])488H1160IA32_VMX_CR4_FIXED03, 4, 6UniqueCapability Reporting Register ofCR4 Bits Fixed to 0. (R/O)See Appendix G.7, “VMX-Fixed Bitsin CR4”(If CPUID.01H:ECX.[bit 9])489H1161IA32_VMX_CR4_FIXED13, 4, 6UniqueCapability Reporting Register ofCR4 Bits Fixed to 1. (R/O)See Appendix G.7, “VMX-Fixed Bitsin CR4”(If CPUID.01H:ECX.[bit 9])48AH1162IA32_VMX_VMCS_ENUM3, 4, 6UniqueCapability Reporting Register ofVMCS Field Enumeration.
(R/O).See Appendix G.8, “VMCSEnumeration”(If CPUID.01H:ECX.[bit 9])B-66 Vol. 3MODEL-SPECIFIC REGISTERS (MSRS)Table B-2. MSRs in the Pentium 4 and Intel Xeon Processors (Contd.)RegisterAddressHexDec48BH1163Register NameFields and FlagsModelAvailabilityShared/Unique1IA32_VMX_PROCBASED_CTLS23, 4, 6UniqueBit DescriptionCapability Reporting Register ofSecondary Processor-basedVM-execution Controls. (R/O)See Appendix G.2, “VM-ExecutionControls”(If CPUID.01H:ECX.[bit 9] andIA32_VMX_PROCBASED_CTLS[bit63])600H1536IA32_DS_AREA0, 1, 2,3, 4, 6UniqueDS Save Area. (R/W)Points to the DS buffermanagement area, which is usedto manage the BTS and PEBSbuffers.See Section 18.15.4, “Debug Store(DS) Mechanism.”31:0DS Buffer Management Area.Linear address of the first byte ofthe DS buffer management area.63:32600H1536Reserved.63:0UniqueDS Buffer Management Area.Linear address of the first byte ofthe DS buffer management area(If IA-32e mode is active).680H1664MSR_LASTBRANCH_0_FROM_LIP3, 4, 6UniqueLast Branch Record 0.
(R/W)One of 16 pairs of last branchrecord registers on the last branchrecord stack (680H-68FH). Thispart of the stack contains pointersto the source instruction for oneof the last 16 branches,exceptions, or interrupts taken bythe processor.Vol. 3 B-67MODEL-SPECIFIC REGISTERS (MSRS)Table B-2. MSRs in the Pentium 4 and Intel Xeon Processors (Contd.)RegisterAddressHexRegister NameFields and FlagsDecModelAvailabilityShared/Unique1Bit DescriptionThe MSRs at 680H-68FH, 6C0H6CfH are not available in processorreleases before family 0FH, model03H. These MSRs replace MSRspreviously located at 1DBH1DEH.which performed the samefunction for early releases.See Section 18.6, “Last Branch,Interrupt, and Exception Recording(Processors based on IntelNetBurst® Microarchitecture).”681H682H683H684H685H686H687H688H16651666166716681669167016711672B-68 Vol.
3MSR_LASTBRANCH_1_FROM_LIP3, 4, 6MSR_LASTBRANCH_2_FROM_LIP3, 4, 6MSR_LASTBRANCH_3_FROM_LIP3, 4, 6MSR_LASTBRANCH_4_FROM_LIP3, 4, 6MSR_LASTBRANCH_5_FROM_LIP3, 4, 6MSR_LASTBRANCH_6_FROM_LIP3, 4, 6MSR_LASTBRANCH_7_FROM_LIP3, 4, 6MSR_LASTBRANCH_8_FROM_LIP3, 4, 6UniqueLast Branch Record 1.See description ofMSR_LASTBRANCH_0 at 680H.UniqueLast Branch Record 2.See description ofMSR_LASTBRANCH_0 at 680H.UniqueLast Branch Record 3.See description ofMSR_LASTBRANCH_0 at 680H.UniqueLast Branch Record 4.See description ofMSR_LASTBRANCH_0 at 680H.UniqueLast Branch Record 5.See description ofMSR_LASTBRANCH_0 at 680H.UniqueLast Branch Record 6.See description ofMSR_LASTBRANCH_0 at 680H.UniqueLast Branch Record 7.See description ofMSR_LASTBRANCH_0 at 680H.UniqueLast Branch Record 8.See description ofMSR_LASTBRANCH_0 at 680H.MODEL-SPECIFIC REGISTERS (MSRS)Table B-2.
MSRs in the Pentium 4 and Intel Xeon Processors (Contd.)RegisterAddressHexDec689H167368AH68BH68CH68DH68EH68FH6C0H1674167516761677167816791728Register NameFields and FlagsModelAvailabilityShared/Unique1MSR_LASTBRANCH_9_FROM_LIP3, 4, 6UniqueMSR_LASTBRANCH_10_FROM_LIP3, 4, 6MSR_LASTBRANCH_11_FROM_LIP3, 4, 6MSR_LASTBRANCH_12_FROM_LIP3, 4, 6MSR_LASTBRANCH_13_FROM_LIP3, 4, 6MSR_LASTBRANCH_14_FROM_LIP3, 4, 6MSR_LASTBRANCH_15_FROM_LIP3, 4, 6MSR_LASTBRANCH_0_TO_LIP3, 4, 6Bit DescriptionLast Branch Record 9.See description ofMSR_LASTBRANCH_0 at 680H.UniqueLast Branch Record 10.See description ofMSR_LASTBRANCH_0 at 680H.UniqueLast Branch Record 11.See description ofMSR_LASTBRANCH_0 at 680H.UniqueLast Branch Record 12.See description ofMSR_LASTBRANCH_0 at 680H.UniqueLast Branch Record 13.See description ofMSR_LASTBRANCH_0 at 680H.UniqueLast Branch Record 14.See description ofMSR_LASTBRANCH_0 at 680H.UniqueLast Branch Record 15.See description ofMSR_LASTBRANCH_0 at 680H.UniqueLast Branch Record 0.
(R/W)One of 16 pairs of last branchrecord registers on the last branchrecord stack (6C0H-6CFH). Thispart of the stack contains pointersto the destination instruction forone of the last 16 branches,exceptions, or interrupts that theprocessor took.See Section 18.6, “Last Branch,Interrupt, and Exception Recording(Processors based on IntelNetBurst® Microarchitecture).”Vol.
3 B-69MODEL-SPECIFIC REGISTERS (MSRS)Table B-2. MSRs in the Pentium 4 and Intel Xeon Processors (Contd.)RegisterAddressHexDec6C1H17296C2H6C3H6C4H6C5H6C6H6C7H6C8H6C9H6CAH6CBH1730173117321733173417351736173717381739B-70 Vol. 3Register NameFields and FlagsModelAvailabilityShared/Unique1MSR_LASTBRANCH_1_TO_LIP3, 4, 6UniqueMSR_LASTBRANCH_2_TO_LIP3, 4, 6MSR_LASTBRANCH_3_TO_LIP3, 4, 6MSR_LASTBRANCH_4_TO_LIP3, 4, 6MSR_LASTBRANCH_5_TO_LIP3, 4, 6MSR_LASTBRANCH_6_TO_LIP3, 4, 6MSR_LASTBRANCH_7_TO_LIP3, 4, 6MSR_LASTBRANCH_8_TO_LIP3, 4, 6MSR_LASTBRANCH_9_TO_LIP3, 4, 6MSR_LASTBRANCH_10_TO_LIP3, 4, 6MSR_LASTBRANCH_11_TO_LIP3, 4, 6Bit DescriptionLast Branch Record 1.See description ofMSR_LASTBRANCH_0 at 6C0H.UniqueLast Branch Record 2.See description ofMSR_LASTBRANCH_0 at 6C0H.UniqueLast Branch Record 3.See description ofMSR_LASTBRANCH_0 at 6C0H.UniqueLast Branch Record 4.See description ofMSR_LASTBRANCH_0 at 6C0H.UniqueLast Branch Record 5.See description ofMSR_LASTBRANCH_0 at 6C0H.UniqueLast Branch Record 6.See description ofMSR_LASTBRANCH_0 at 6C0H.UniqueLast Branch Record 7.See description ofMSR_LASTBRANCH_0 at 6C0H.UniqueLast Branch Record 8.See description ofMSR_LASTBRANCH_0 at 6C0H.UniqueLast Branch Record 9.See description ofMSR_LASTBRANCH_0 at 6C0H.UniqueLast Branch Record 10.See description ofMSR_LASTBRANCH_0 at 6C0H.UniqueLast Branch Record 11.See description ofMSR_LASTBRANCH_0 at 6C0H.MODEL-SPECIFIC REGISTERS (MSRS)Table B-2.
MSRs in the Pentium 4 and Intel Xeon Processors (Contd.)RegisterAddressHexDec6CCH17406CDH6CEH6CFHC000_0080H174117421743Register NameFields and FlagsModelAvailabilityShared/Unique1MSR_LASTBRANCH_12_TO_LIP3, 4, 6UniqueMSR_LASTBRANCH_13_TO_LIP3, 4, 6MSR_LASTBRANCH_14_TO_LIP3, 4, 6MSR_LASTBRANCH_15_TO_LIP3, 4, 6IA32_EFER3, 4, 6Bit DescriptionLast Branch Record 12.See description ofMSR_LASTBRANCH_0 at 6C0H.UniqueLast Branch Record 13.See description ofMSR_LASTBRANCH_0 at 6C0H.UniqueLast Branch Record 14.See description ofMSR_LASTBRANCH_0 at 6C0H.UniqueLast Branch Record 15.See description ofMSR_LASTBRANCH_0 at 6C0H.UniqueExtended Feature Enables.(If CPUID.80000001.EDX.[bit 20]or CPUID.80000001.EDX.[bit29])0SYSCALL Enable (R/W).Enables SYSCALL/SYSRETinstructions in 64-bit mode.7:1Reserved.8IA-32e Mode Enable.
(R/W).Enables IA-32e mode operation.9Reserved.10IA-32e Mode Active. (R)Indicates IA-32e mode is activewhen set.11Execute Disable Bit Enable.(R/W)Enables the Execute-Disable-Bitfunctionality in paging structures.63:12C000_0081HIA32_STARReserved.3, 4, 6UniqueSystem Call Target Address.(R/W)(If CPUID.80000001.EDX.[bit 29])Vol. 3 B-71MODEL-SPECIFIC REGISTERS (MSRS)Table B-2. MSRs in the Pentium 4 and Intel Xeon Processors (Contd.)RegisterAddressHexRegister NameFields and FlagsDecModelAvailabilityShared/Unique1C000_0082HIA32_LSTAR3, 4, 6UniqueC000_0084HIA32_FMASK3, 4, 6UniqueC000_0100HIA32_FS_BASEBit DescriptionIA-32e Mode System Call TargetAddress.
(R/W)(If CPUID.80000001.EDX.[bit 29])System Call Flag Mask. (R/W)(If CPUID.80000001.EDX.[bit 29])3, 4, 6UniqueMap of BASE Address of FS.(R/W)(If CPUID.80000001.EDX.[bit 29])C000_0101HIA32_GS_BASE3, 4, 6UniqueC000_0102HIA32_KERNEL_GSBASE3, 4, 6UniqueMap of BASE Address of GS.(R/W)(If CPUID.80000001.EDX.[bit 29])Swap Target of BASE Address ofGS. (R/W)(If CPUID.80000001.EDX.[bit 29])NOTES1.
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