Volume 3B System Programming Guide_ Part 2 (794104), страница 100
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For HT-enabled processors, there may be more than one logical processors per physical unit. Ifan MSR is Shared, this means that one MSR is shared between logical processors. If an MSR isunique, this means that each logical processor has its own MSR.B.2.1MSRs Unique to Intel Xeon Processor MP with L3 CacheThe MSRs listed in Table B-3 apply to Intel Xeon Processor MP with up to 8MB levelthree cache. These processors can be detected by enumerating the deterministiccache parameter leaf of CPUID instruction (with EAX = 4 as input) to detect the presence of the third level cache, and with CPUID reporting family encoding 0FH, modelencoding 3 or 4 (See CPUID instruction for more details.).B-72 Vol. 3MODEL-SPECIFIC REGISTERS (MSRS)Table B-3.
MSRs Unique to 64-bit Intel Xeon Processor MP withUp to an 8 MB L3 CacheRegister Address107CCHRegister NameFields and FlagsMSR_IFSB_BUSQ0ModelAvailability3, 4Shared/UniqueSharedBit DescriptionIFSB BUSQ Event Controland Counter Register.(R/W)See Section 18.19,“Performance Monitoring on64-bit Intel Xeon ProcessorMP with Up to 8-MByte L3Cache.”107CDHMSR_IFSB_BUSQ13, 4SharedIFSB BUSQ Event Controland Counter Register.(R/W)107CEHMSR_IFSB_SNPQ03, 4SharedIFSB SNPQ Event Controland Counter Register.(R/W)See Section 18.19,“Performance Monitoring on64-bit Intel Xeon ProcessorMP with Up to 8-MByte L3Cache.”107CFHMSR_IFSB_SNPQ13, 4SharedIFSB SNPQ Event Controland Counter Register.(R/W)107D0HMSR_EFSB_DRDY03, 4SharedEFSB DRDY Event Controland Counter Register.(R/W)See Section 18.19,“Performance Monitoring on64-bit Intel Xeon ProcessorMP with Up to 8-MByte L3Cache” for details.107D1HMSR_EFSB_DRDY13, 4SharedEFSB DRDY Event Controland Counter Register.(R/W)Vol.
3 B-73MODEL-SPECIFIC REGISTERS (MSRS)Table B-3. MSRs Unique to 64-bit Intel Xeon Processor MP withUp to an 8 MB L3 Cache (Contd.)Register Address107D2HRegister NameFields and FlagsMSR_IFSB_CTL6ModelAvailability3, 4Shared/UniqueSharedBit DescriptionIFSB Latency Event ControlRegister. (R/W)See Section 18.19,“Performance Monitoring on64-bit Intel Xeon ProcessorMP with Up to 8-MByte L3Cache” for details.107D3HMSR_IFSB_CNTR73, 4SharedIFSB Latency EventCounter Register. (R/W)See Section 18.19,“Performance Monitoring on64-bit Intel Xeon ProcessorMP with Up to 8-MByte L3Cache.”The MSRs listed in Table B-4 apply to Intel Xeon Processor 7100 series.
Theseprocessors can be detected by enumerating the deterministic cache parameter leaf ofCPUID instruction (with EAX = 4 as input) to detect the presence of the third levelcache, and with CPUID reporting family encoding 0FH, model encoding 6 (See CPUIDinstruction for more details.).
The performance monitoring MSRs listed in Table B-4are shared between logical processors in the same core, but are replicated for eachcore.Table B-4. MSRs Unique to Intel Xeon Processor 7100 SeriesRegister Address107CCHRegister NameFields and FlagsMSR_EMON_L3_CTR_CTL0ModelAvailability6Shared/UniqueSharedBit DescriptionGBUSQ Event Control andCounter Register.
(R/W)See Section 18.20,“Performance Monitoring onDual-Core Intel XeonProcessor 7100 Series.”107CDHB-74 Vol. 3MSR_EMON_L3_CTR_CTL16SharedGBUSQ Event Control andCounter Register. (R/W)MODEL-SPECIFIC REGISTERS (MSRS)Table B-4. MSRs Unique to Intel Xeon Processor 7100 Series (Contd.)Register Address107CEHRegister NameFields and FlagsMSR_EMON_L3_CTR_CTL2ModelAvailability6Shared/UniqueSharedBit DescriptionGSNPQ Event Control andCounter Register. (R/W)See Section 18.20,“Performance Monitoring onDual-Core Intel XeonProcessor 7100 Series.”107CFHMSR_EMON_L3_CTR_CTL36SharedGSNPQ Event Control andCounter Register (R/W)107D0HMSR_EMON_L3_CTR_CTL46SharedFSB Event Control andCounter Register.
(R/W)See Section 18.20,“Performance Monitoring onDual-Core Intel XeonProcessor 7100 Series” fordetails.107D1HMSR_EMON_L3_CTR_CTL56SharedFSB Event Control andCounter Register. (R/W)107D2HMSR_EMON_L3_CTR_CTL66SharedFSB Event Control andCounter Register. (R/W)107D3HMSR_EMON_L3_CTR_CTL76SharedFSB Event Control andCounter Register.
(R/W)B.3MSRS IN INTEL® CORE™ SOLO AND INTEL® CORE™DUO PROCESSORSModel-specific registers (MSRs) for Intel Core Solo, Intel Core Duo processors, andDual-core Intel Xeon processor LV are listed in Table B-5. The column“Shared/Unique”applies to Intel Core Duo processor. “Unique” means each processorcore has a separate MSR, or a bit field in an MSR governs only a core independently.“Shared” means the MSR or the bit field in an MSR address governs the operation ofboth processor cores.Vol. 3 B-75MODEL-SPECIFIC REGISTERS (MSRS)Table B-5. MSRs in Intel Core Solo, Intel Core Duo Processors, and Dual-core IntelXeon Processor LVRegisterAddressRegister NameShared/UniqueBit DescriptionHexDec0H0P5_MC_ADDRUniqueSee Appendix B.6, “MSRs in PentiumProcessors.”1H1P5_MC_TYPEUniqueSee Appendix B.6, “MSRs in PentiumProcessors.”6H6IA32_MONITOR_FILTER_SIZEUniqueSee Section 7.11.5, “Monitor/Mwait AddressRange Determination.”10H16IA32_TIME_STAMP_COUNTERUniqueSee Section 18.10, “Time-Stamp Counter.”17H23IA32_PLATFORM_IDSharedPlatform ID.
(R)The operating system can use this MSR todetermine “slot” information for the processorand the proper microcode update to load.49:0Reserved.52:50Platform Id. (R)Contains information concerning the intendedplatform for the processor.520000111163:5351001100115001010101Processor Flag 0Processor Flag 1Processor Flag 2Processor Flag 3Processor Flag 4Processor Flag 5Processor Flag 6Processor Flag 7Reserved.1BH27IA32_APIC_BASEUniqueSee Section 8.4.4, “Local APIC Status andLocation.”2AH42MSR_EBL_CR_POWERONSharedProcessor Hard Power-On Configuration.(R/W)Enables and disables processor features; (R)indicates current processor configuration.0B-76 Vol. 3Reserved.MODEL-SPECIFIC REGISTERS (MSRS)Table B-5. MSRs in Intel Core Solo, Intel Core Duo Processors, and Dual-core IntelXeon Processor LV (Contd.)RegisterAddressHexRegister NameShared/UniqueBit DescriptionDec1Data Error Checking Enable.
(R/W)1 = Enabled0 = DisabledAlways 0 on the Pentium M processor.2Response Error Checking Enable. (R/W)FRCERR Observation Enable:1 = Enabled0 = DisabledAlways 0 on the Pentium M processor.3AERR# Drive Enable. (R/W)1 = Enabled0 = DisabledAlways 0 on the Pentium M processor.4BERR# Enable for initiator bus requests.(R/W)1 = Enabled0 = DisabledAlways 0 on the Pentium M processor.5Reserved6BERR# Driver Enable for initiator internalerrors. (R/W)1 = Enabled0 = DisabledAlways 0 on the Pentium M processor.7BINIT# Driver Enable. (R/W)1 = Enabled0 = DisabledAlways 0 on the Pentium M processor.8Output Tri-state Enabled.
(R/O)1 = Enabled0 = DisabledVol. 3 B-77MODEL-SPECIFIC REGISTERS (MSRS)Table B-5. MSRs in Intel Core Solo, Intel Core Duo Processors, and Dual-core IntelXeon Processor LV (Contd.)RegisterAddressHexRegister NameShared/UniqueBit DescriptionDec9Execute BIST. (R/O)1 = Enabled0 = Disabled10AERR# Observation Enabled. (R/O)1 = Enabled0 = DisabledAlways 0 on the Pentium M processor.11Reserved12BINIT# Observation Enabled. (R/O)1 = Enabled0 = DisabledAlways 0 on the Pentium M processor.13In Order Queue Depth. (R/O)1=10=8141 MByte Power on Reset Vector. (R/O)1 = 1 MByte0 = 4 GBytesAlways 0 on the Pentium M processor.15Reserved17:16APIC Cluster ID. (R/O)Always 00B on the Pentium M processor.18System Bus Frequency.
(R/O)0 = 100 MHz1 = ReservedAlways 0 on the Pentium M processor.19Reserved.21: 20Symmetric Arbitration ID. (R/O)Always 00B on the Pentium M processor.26:22B-78 Vol. 3Clock Frequency Ratio. (R/O)MODEL-SPECIFIC REGISTERS (MSRS)Table B-5. MSRs in Intel Core Solo, Intel Core Duo Processors, and Dual-core IntelXeon Processor LV (Contd.)RegisterAddressHexDec3AH5840H64Register NameShared/UniqueIA32_FEATURE_CONTROLUniqueMSR_LASTBRANCH_0UniqueBit DescriptionControl Features in IA-32 Processor. (R/W)(If CPUID.1.ECX.[bit 5])Last Branch Record 0. (R/W)One of 8 last branch record registers on thelast branch record stack: bits 31-0 hold the‘from’ address and bits 63-32 hold the ‘to’address. See also:• Last Branch Record Stack TOS at 1C9H• Section 18.8, “Last Branch, Interrupt, andException Recording (Pentium MProcessors).”41H42H43H44H45H46H47H65666768697071MSR_LASTBRANCH_1UniqueMSR_LASTBRANCH_2UniqueMSR_LASTBRANCH_3UniqueMSR_LASTBRANCH_4UniqueMSR_LASTBRANCH_5UniqueMSR_LASTBRANCH_6UniqueMSR_LASTBRANCH_7UniqueLast Branch Record 1.
(R/W)See description of MSR_LASTBRANCH_0.Last Branch Record 2. (R/W)See description of MSR_LASTBRANCH_0.Last Branch Record 3. (R/W)See description of MSR_LASTBRANCH_0.Last Branch Record 4. (R/W)See description of MSR_LASTBRANCH_0.Last Branch Record 5. (R/W)See description of MSR_LASTBRANCH_0.Last Branch Record 6. (R/W)See description of MSR_LASTBRANCH_0.Last Branch Record 7. (R/W)See description of MSR_LASTBRANCH_0.79H121IA32_BIOS_UPDT_TRIGUniqueBIOS Update Trigger Register (R/W)8BH139IA32_BIOS_SIGN_IDUniqueBIOS Update Signature ID (RO)C1H193IA32_PMC0UniquePerformance counter register.Vol.
3 B-79MODEL-SPECIFIC REGISTERS (MSRS)Table B-5. MSRs in Intel Core Solo, Intel Core Duo Processors, and Dual-core IntelXeon Processor LV (Contd.)RegisterAddressRegister NameShared/UniqueBit DescriptionHexDecC2H194IA32_PMC1UniquePerformance counter register.CDH205MSR_FSB_FREQSharedScaleable Bus Speed. (RO)This field indicates the scaleable bus clockspeed:2:0• 101B: 100 MHz (FSB 400)• 001B: 133 MHz (FSB 533)• 011B: 167 MHz (FSB 667)133.33 MHz should be utilized if performingcalculation with System Bus Speed whenencoding is 101B.166.67 MHz should be utilized if performingcalculation with System Bus Speed whenencoding is 001B.63:3E7H231IA32_MPERFReservedUnique63:0Maximum Performance Frequency ClockCount.
(RW)C0_MCNT: C0 Maximum Frequency ClockCount.Increments at maximum clock frequencydivided by 1024 (as allowed by the ResolvedRatio) when core is in C0. Cleared by a write tothe MCNT, the ACNT and upon overflow/wraparound of this counter.E8H232IA32_APERF63:0UniqueActual Performance Frequency Clock Count.(RW)C0_ACNT: C0 Actual Frequency Clock Count.Accumulates core clock counts - at thecoordinated clock frequency - divided by1024, when core is in C0. Cleared by a write tothis field or the MCNTB-80 Vol. 3MODEL-SPECIFIC REGISTERS (MSRS)Table B-5.
MSRs in Intel Core Solo, Intel Core Duo Processors, and Dual-core IntelXeon Processor LV (Contd.)RegisterAddressRegister NameShared/UniqueHexDecFEH254IA32_MTRRCAPUnique11EH281MSR_BBL_CR_CTL3Shared0Bit DescriptionL2 Hardware Enabled. (RO)1 = If the L2 is hardware-enabled0 = Indicates if the L2 is hardware-disabled4:1Reserved.5ECC Check Enable.
(RO)This bit enables ECC checking on the cachedata bus. ECC is always generated on writecycles.0 = Disabled (default)1 = Enabled7:6Reserved.8L2 Enabled. (R/W)1 = L2 cache has been initialized0 = Disabled (default)Until this bit is set the processor will notrespond to the WBINVD instruction or theassertion of the FLUSH# input.22:9Reserved.23L2 Not Present. (RO)0 = L2 Present1 = L2 Not Present63:24174H372IA32_SYSENTER_CSReserved.UniqueVol.
3 B-81MODEL-SPECIFIC REGISTERS (MSRS)Table B-5. MSRs in Intel Core Solo, Intel Core Duo Processors, and Dual-core IntelXeon Processor LV (Contd.)RegisterAddressRegister NameShared/UniqueHexDec175H373IA32_SYSENTER_ESPUnique176H374IA32_SYSENTER_EIPUnique179H377IA32_MCG_CAPUnique7:0Bit DescriptionCount. (RO)Indicates the number of hardware unit errorreporting banks available in the processor8IA32_MCG_CTL Present. (RO)1=0=63:917AH378IA32_MCG_STATUS0Indicates that the processor implementsthe MSR_MCG_CTL register found atMSR 17BH.Not supported.Reserved.UniqueRIPV.When set, this bit indicates that theinstruction addressed by the instructionpointer pushed on the stack (when themachine check was generated) can be used torestart the program. If this bit is cleared, theprogram cannot be reliably restarted1EIPV.When set, this bit indicates that theinstruction addressed by the instructionpointer pushed on the stack (when themachine check was generated) is directlyassociated with the error.B-82 Vol.
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