Volume 3B System Programming Guide_ Part 2 (794104), страница 101
Текст из файла (страница 101)
3MODEL-SPECIFIC REGISTERS (MSRS)Table B-5. MSRs in Intel Core Solo, Intel Core Duo Processors, and Dual-core IntelXeon Processor LV (Contd.)RegisterAddressHexRegister NameShared/UniqueBit DescriptionDec2MCIP.When set, this bit indicates that a machinecheck has been generated. If a secondmachine check is detected while this bit is stillset, the processor enters a shutdown state.Software should write this bit to 0 afterprocessing a machine check exception.63:3Reserved.186H390IA32_PERFEVTSEL0Unique187H391IA32_PERFEVTSEL1Unique198H408IA32_PERF_STATShared199H19AH409410See15:0Current Performance State Value.63:16Reserved.IA32_PERF_CTLUnique15:0Target Performance State Value.63:16Reserved.IA32_CLOCK_MODULATIONUniqueClock Modulation.
(R/W)Enables and disables on-demand clockmodulation and allows the selection of the ondemand clock modulation duty cycle. SeeSection 13.5.3, “Software Controlled ClockModulation.”IA32_CLOCK_MODULATION MSR wasoriginally named IA32_THERM_CONTROLMSR.19BH411IA32_THERM_INTERRUPTUniqueThermal Interrupt Control. (R/W)Enables and disables the generation of aninterrupt on temperature transitions detectedwith the processor’s thermal sensors andthermal monitor.See Section 13.5.2, “Thermal Monitor.”Vol.
3 B-83MODEL-SPECIFIC REGISTERS (MSRS)Table B-5. MSRs in Intel Core Solo, Intel Core Duo Processors, and Dual-core IntelXeon Processor LV (Contd.)RegisterAddressHexDec19CH412Register NameIA32_THERM_STATUSShared/UniqueUniqueBit DescriptionThermal Monitor Status. (R/W)Contains status information about theprocessor’s thermal sensor and automaticthermal monitoring facilities.See Section 13.5.2, “Thermal Monitor”.19DH413MSR_THERM2_CTLUnique15:0Reserved.16TM_SELECT. (R/W)Mode of automatic thermal monitor:0 = Thermal Monitor 1 (thermally-initiatedon-die modulation of the stop-clock dutycycle)1 = Thermal Monitor 2 (thermally-initiatedfrequency transitions)If bit 3 of the IA32_MISC_ENABLE register iscleared, TM_SELECT has no effect. NeitherTM1 nor TM2 will be enabled.1A0B-84 Vol.
341663:16Reserved.IA32_MISC_ENABLEEnable Miscellaneous Processor Features.2:0Reserved.(R/W) Allows a variety of processor functionsto be enabled and disabled.MODEL-SPECIFIC REGISTERS (MSRS)Table B-5. MSRs in Intel Core Solo, Intel Core Duo Processors, and Dual-core IntelXeon Processor LV (Contd.)RegisterAddressHexRegister NameShared/UniqueBit DescriptionDec3UniqueAutomatic Thermal Control Circuit Enable.(R/W)1 = Setting this bit enables the thermalcontrol circuit (TCC) portion of the IntelThermal Monitor feature.
This allowsprocessor clocks to be automaticallymodulated based on the processor'sthermal sensor operation.0 = Disabled (default).The automatic thermal control circuit enablebit determines if the thermal control circuit(TCC) will be activated when the processor'sinternal thermal sensor determines theprocessor is about to exceed its maximumoperating temperature.When the TCC is activated and TM1 is enabled,the processors clocks will be forced to a 50%duty cycle.
BIOS must enable this feature.The bit should not be confused with the ondemand thermal control circuit enable bit.6:47ReservedSharedPerformance Monitoring Available. (R)1=0=9:810Performance monitoring enabledPerformance monitoring disabledReservedSharedFERR# Multiplexing Enable. (R/W)1=FERR# asserted by the processor toindicate a pending break event withinthe processor0 = Indicates compatible FERR# signalingbehaviorThis bit must be set to 1 to support XAPICinterrupt model usage.Vol.
3 B-85MODEL-SPECIFIC REGISTERS (MSRS)Table B-5. MSRs in Intel Core Solo, Intel Core Duo Processors, and Dual-core IntelXeon Processor LV (Contd.)RegisterAddressHexRegister NameShared/UniqueBit DescriptionDec11SharedBranch Trace Storage Unavailable. (RO)1 =Processor doesn’t support branch tracestorage (BTS)0 =BTS is supported12SharedPrecise Event Based Sampling Unavailable.(RO)1=Processor does not support preciseevent-based sampling (PEBS);0 = PEBS is supported.The Intel Core Solo and Intel Core Duoprocessors do not support PEBS.13SharedTM2 Enable. (R/W)When this bit is set (1) and the thermal sensorindicates that the die temperature is at thepre-determined threshold, the ThermalMonitor 2 mechanism is engaged.
TM2 willreduce the bus to core ratio and voltageaccording to the value last written toMSR_THERM2_CTL bits 15:0.When this bit is clear (0, default), theprocessor does not change the VID signals orthe bus to core ratio when the processorenters a thermal managed state.If the TM2 feature flag (ECX[8]) is not set to 1after executing CPUID with EAX = 1, then thisfeature is not supported and BIOS must notalter the contents of this bit location. Theprocessor is operating out of spec if both thisbit and the TM1 bit are set to disabled states.15:1416ReservedSharedEnhanced Intel SpeedStep TechnologyEnable.
(R/W)1=B-86 Vol. 3Enhanced Intel SpeedStep TechnologyenabledMODEL-SPECIFIC REGISTERS (MSRS)Table B-5. MSRs in Intel Core Solo, Intel Core Duo Processors, and Dual-core IntelXeon Processor LV (Contd.)RegisterAddressHexRegister NameShared/UniqueBit DescriptionDec18SharedENABLE MONITOR FSM. (R/W)When this bit is set to 0, the MONITOR featureflag ECX[3] returned by CPUID.01H is set to 0.This indicates that MONITOR/MWAIT are notsupported. An Illegal Instruction exception isgenerated if software attempts to executeMONITOR/MWAIT when this bit is 0.When this bit is set to 1 (default),MONITOR/MWAIT are supported andCPUID.01H:ECX[bit 3] = 1.If the Streaming SIMD Extensions 3 (SSE3)feature flag ECX[0] is not set, the OS must notattempt to alter this bit.
BIOS should leavethis bit in the default state. Writing this bitwhen the SSE3 feature flag is set to 0 maygenerate a #GP exception.1922Reserved.SharedLimit CPUID Maxval. (R/W)When this bit is set to 1, CPUID.00H returns amaximum value in EAX[7:0] of 3. When set toa 0 (default), CPUID.00H returns the numberof the maximum standard function supportedin EAX[7:0].BIOS should contain a setup question thatallows users to specify when the installed OSdoes not support CPUID functions > 3.Before setting this bit, BIOS must execute theCPUID instruction with EAX = 0 and examinethe maximum value returned in EAX[7:0].
Ifthe maximum value is > 3, the bit issupported. Otherwise, the bit is notsupported. Writing to this bit when themaximum value is < 3 may generate a #GPexception.Setting this bit may cause behavior insoftware that depends on the availability ofCPUID leaves greater than 3.Vol. 3 B-87MODEL-SPECIFIC REGISTERS (MSRS)Table B-5. MSRs in Intel Core Solo, Intel Core Duo Processors, and Dual-core IntelXeon Processor LV (Contd.)RegisterAddressHexRegister NameShared/UniqueBit DescriptionDec33:2334Reserved.SharedXD Bit Disable.
(R/W)When set to 1, the Execute Disable Bit feature(XD Bit) is disabled and the XD Bit extendedfeature flag will be clear (CPUID.80000001H:EDX[20]=0).When set to a 0 (default), the Execute DisableBit feature (if available) allows the OS toenable PAE paging and take advantage of dataonly pages.Assuming this bit is not set to 1 and ifCPUID.80000001H: EDX[20]=0, this feature isnot supported and BIOS must not alter thecontents of this bit location. Writing this bit to1 when the XD Bit extended feature flag isset to 0 may generate a #GP exception.63:351C9H457MSR_LASTBRANCH_TOSReserved.UniqueLast Branch Record Stack TOS. (R)Contains an index (bits 0-3) that points to theMSR containing the most recent branch record.See MSR_LASTBRANCH_0 (at 40H)1D9H473IA32_DEBUGCTLUniqueDebug Control.
(R/W)Controls how several debug features are used.Bit definitions are discussed in the referencedsection.1DDH1DEH477478MSR_LER_FROM_LIPUniqueMSR_LER_TO_LIPUniqueLast Exception Record From Linear IP. (R)Contains a pointer to the last branchinstruction that the processor executed priorto the last exception that was generated orthe last interrupt that was handled.Last Exception Record To Linear IP. (R)This area contains a pointer to the target ofthe last branch instruction that the processorexecuted prior to the last exception that wasgenerated or the last interrupt that washandled.B-88 Vol. 3MODEL-SPECIFIC REGISTERS (MSRS)Table B-5.
MSRs in Intel Core Solo, Intel Core Duo Processors, and Dual-core IntelXeon Processor LV (Contd.)RegisterAddressHexDec1E0H480Register NameROB_CR_BKUPTMPDR6Shared/UniqueBit DescriptionUnique1:0Reserved2Fast String Enable bit. (Default, enabled)200H512MTRRphysBase0Unique201H513MTRRphysMask0Unique202H514MTRRphysBase1Unique203H515MTRRphysMask1Unique204H516MTRRphysBase2Unique205H517MTRRphysMask2Unique206H518MTRRphysBase3Unique207H519MTRRphysMask3Unique208H520MTRRphysBase4Unique209H521MTRRphysMask4Unique20AH522MTRRphysBase5Unique20BH523MTRRphysMask5Unique20CH524MTRRphysBase6Unique20DH525MTRRphysMask6Unique20EH526MTRRphysBase7Unique20FH527MTRRphysMask7Unique250H592MTRRfix64K_00000Unique258H600MTRRfix16K_80000Unique259H601MTRRfix16K_A0000Unique268H616MTRRfix4K_C0000Unique269H617MTRRfix4K_C8000UniqueVol.
3 B-89MODEL-SPECIFIC REGISTERS (MSRS)Table B-5. MSRs in Intel Core Solo, Intel Core Duo Processors, and Dual-core IntelXeon Processor LV (Contd.)RegisterAddressRegister NameShared/UniqueHexDec26AH618MTRRfix4K_D0000Unique26BH619MTRRfix4K_D8000Unique26CH620MTRRfix4K_E0000Unique26DH621MTRRfix4K_E8000Unique26EH622MTRRfix4K_F0000Unique26FH623MTRRfix4K_F8000Unique2FFH767IA32_MTRR_DEF_TYPEUniqueBit DescriptionDefault Memory Types. (R/W)Sets the memory type for the regions ofphysical memory that are not mapped by theMTRRs.See Section 10.11.2.1,“IA32_MTRR_DEF_TYPE MSR.”400H1024IA32_MC0_CTLUniqueSee Section 14.3.2.1, “IA32_MCi_CTL MSRs.”401H1025IA32_MC0_STATUSUniqueSee Section 14.3.2.2, “IA32_MCi_STATUSMSRS.”402H1026IA32_MC0_ADDRUniqueSee Section 14.3.2.3, “IA32_MCi_ADDR MSRs.”The IA32_MC0_ADDR register is either notimplemented or contains no address if theADDRV flag in the IA32_MC0_STATUS registeris clear.
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