Volume 3A System Programming Guide_ Part 1 (794103), страница 30
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The NE flag, IGNNE# pin, and FERR# pinare used with external logic to implement PC-style error reporting.See also: “Software Exception Handling” in Chapter 8, “Programming withthe x87 FPU,” and Appendix A, “Eflags Cross-Reference,” in the Intel® 64and IA-32 Architectures Software Developer’s Manual, Volume 1.ETExtension Type (bit 4 of CR0) — Reserved in the Pentium 4, Intel Xeon, P6family, and Pentium processors. In the Pentium 4, Intel Xeon, and P6 familyprocessors, this flag is hardcoded to 1. In the Intel386 and Intel486 processors, this flag indicates support of Intel 387 DX math coprocessor instructions when set.TSTask Switched (bit 3 of CR0) — Allows the saving of the x87FPU/MMX/SSE/SSE2/ SSE3 context on a task switch to be delayed until anx87 FPU/MMX/SSE/SSE2/SSE3 instruction is actually executed by the newtask.
The processor sets this flag on every task switch and tests it whenexecuting x87 FPU/MMX/SSE/SSE2/SSE3 instructions.2-20 Vol. 3SYSTEM ARCHITECTURE OVERVIEW•If the TS flag is set and the EM flag (bit 2 of CR0) is clear, a device-notavailable exception (#NM) is raised prior to the execution of any x87FPU/MMX/SSE/ SSE2/SSE3 instruction; with the exception of PAUSE,PREFETCHh, SFENCE, LFENCE, MFENCE, MOVNTI, and CLFLUSH. See theparagraph below for the special case of the WAIT/FWAIT instructions.•If the TS flag is set and the MP flag (bit 1 of CR0) and EM flag are clear, an#NM exception is not raised prior to the execution of an x87 FPUWAIT/FWAIT instruction.•If the EM flag is set, the setting of the TS flag has no affect on theexecution of x87 FPU/MMX/SSE/SSE2/SSE3 instructions.Table 2-1 shows the actions taken when the processor encounters an x87FPU instruction based on the settings of the TS, EM, and MP flags.
Table 11-1and 12-1 show the actions taken when the processor encounters anMMX/SSE/SSE2/SSE3 instruction.The processor does not automatically save the context of the x87 FPU, XMM,and MXCSR registers on a task switch. Instead, it sets the TS flag, whichcauses the processor to raise an #NM exception whenever it encounters anx87 FPU/MMX/SSE /SSE2/SSE3 instruction in the instruction stream for thenew task (with the exception of the instructions listed above).The fault handler for the #NM exception can then be used to clear the TS flag (withthe CLTS instruction) and save the context of the x87 FPU, XMM, and MXCSR registers.
If the task never encounters an x87 FPU/MMX/SSE/SSE2/SSE3 instruction; thex87 FPU/MMX/SSE/SSE2/ SSE3 context is never saved.Table 2-1. Action Taken By x87 FPU Instructions for DifferentCombinations of EM, MP, and TSCR0 Flagsx87 FPU Instruction TypeEMMPTS000ExecuteFloating-PointExecute.WAIT/FWAIT001#NM ExceptionExecute.010ExecuteExecute.011#NM Exception#NM exception.100#NM ExceptionExecute.101#NM ExceptionExecute.110#NM ExceptionExecute.111#NM Exception#NM exception.Vol. 3 2-21SYSTEM ARCHITECTURE OVERVIEWEMEmulation (bit 2 of CR0) — Indicates that the processor does not have aninternal or external x87 FPU when set; indicates an x87 FPU is present whenclear.
This flag also affects the execution of MMX/SSE/SSE2/SSE3 instructions.When the EM flag is set, execution of an x87 FPU instruction generates adevice-not-available exception (#NM). This flag must be set when theprocessor does not have an internal x87 FPU or is not connected to anexternal math coprocessor. Setting this flag forces all floating-point instructions to be handled by software emulation. Table 9-2 shows the recommended setting of this flag, depending on the IA-32 processor and x87 FPUor math coprocessor present in the system. Table 2-1 shows the interactionof the EM, MP, and TS flags.Also, when the EM flag is set, execution of an MMX instruction causes aninvalid-opcode exception (#UD) to be generated (see Table 11-1).
Thus, if anIA-32 or Intel 64 processor incorporates MMX technology, the EM flag mustbe set to 0 to enable execution of MMX instructions.Similarly for SSE/SSE2/SSE3/SSSE3 extensions, when the EM flag is set,execution of most SSE/SSE2/SSE3/SSSE3 instructions causes an invalidopcode exception (#UD) to be generated (see Table 12-1). If an IA-32 orIntel 64 processor incorporates the SSE/SSE2/SSE3/SSSE3 extensions, theEM flag must be set to 0 to enable execution of these extensions.SSE/SSE2/SSE3 instructions not affected by the EM flag include: PAUSE,PREFETCHh, SFENCE, LFENCE, MFENCE, MOVNTI, and CLFLUSH.MPMonitor Coprocessor (bit 1 of CR0). — Controls the interaction of theWAIT (or FWAIT) instruction with the TS flag (bit 3 of CR0).
If the MP flag isset, a WAIT instruction generates a device-not-available exception (#NM) ifthe TS flag is also set. If the MP flag is clear, the WAIT instruction ignores thesetting of the TS flag. Table 9-2 shows the recommended setting of this flag,depending on the IA-32 processor and x87 FPU or math coprocessor presentin the system. Table 2-1 shows the interaction of the MP, EM, and TS flags.PEProtection Enable (bit 0 of CR0) — Enables protected mode when set;enables real-address mode when clear.
This flag does not enable pagingdirectly. It only enables segment-level protection. To enable paging, both thePE and PG flags must be set.See also: Section 9.9, “Mode Switching.”PCDPage-level Cache Disable (bit 4 of CR3) — Controls caching of thecurrent page directory. When the PCD flag is set, caching of the page-directory is prevented; when the flag is clear, the page-directory can be cached.This flag affects only the processor’s internal caches (both L1 and L2, whenpresent). The processor ignores this flag if paging is not used (the PG flag inregister CR0 is clear) or the CD (cache disable) flag in CR0 is set.2-22 Vol.
3SYSTEM ARCHITECTURE OVERVIEWSee also: Chapter 10, “Memory Cache Control” (for more about the use ofthe PCD flag) and Section 3.7.6, “Page-Directory and Page-Table Entries” (fora description of a companion PCD flag in page-directory and page-tableentries).PWTPage-level Writes Transparent (bit 3 of CR3) — Controls the writethrough or write-back caching policy of the current page directory. When thePWT flag is set, write-through caching is enabled; when the flag is clear,write-back caching is enabled. This flag affects only internal caches (both L1and L2, when present). The processor ignores this flag if paging is not used(the PG flag in register CR0 is clear) or the CD (cache disable) flag in CR0 isset.See also: Section 10.5, “Cache Control” (for more information about the useof this flag), and Section 3.7.6, “Page-Directory and Page-Table Entries” (fora description of a companion PCD flag in the page-directory and page-tableentries).VMEVirtual-8086 Mode Extensions (bit 0 of CR4) — Enables interrupt- andexception-handling extensions in virtual-8086 mode when set; disables theextensions when clear.
Use of the virtual mode extensions can improve theperformance of virtual-8086 applications by eliminating the overhead ofcalling the virtual-8086 monitor to handle interrupts and exceptions thatoccur while executing an 8086 program and, instead, redirecting the interrupts and exceptions back to the 8086 program’s handlers. It also provideshardware support for a virtual interrupt flag (VIF) to improve reliability ofrunning 8086 programs in multitasking and multiple-processor environments.See also: Section 15.3, “Interrupt and Exception Handling in Virtual-8086Mode.”PVIProtected-Mode Virtual Interrupts (bit 1 of CR4) — Enables hardwaresupport for a virtual interrupt flag (VIF) in protected mode when set; disablesthe VIF flag in protected mode when clear.See also: Section 15.4, “Protected-Mode Virtual Interrupts.”TSDTime Stamp Disable (bit 2 of CR4) — Restricts the execution of theRDTSC instruction to procedures running at privilege level 0 when set; allowsRDTSC instruction to be executed at any privilege level when clear.DEDebugging Extensions (bit 3 of CR4) — References to debug registersDR4 and DR5 cause an undefined opcode (#UD) exception to be generatedwhen set; when clear, processor aliases references to registers DR4 and DR5for compatibility with software written to run on earlier IA-32 processors.See also: Section 18.2.2, “Debug Registers DR4 and DR5.”PSEPage Size Extensions (bit 4 of CR4) — Enables 4-MByte pages when set;restricts pages to 4 KBytes when clear.See also: Section 3.6.1, “Paging Options.”Vol.
3 2-23SYSTEM ARCHITECTURE OVERVIEWPAEPhysical Address Extension (bit 5 of CR4) — When set, enables pagingmechanism to reference greater-or-equal-than-36-bit physical addresses.When clear, restricts physical addresses to 32 bits. PAE must be enabled toenable IA-32e mode operation. Enabling and disabling IA-32e mode operation also requires modifying CR4.PAE.See also: Section 3.8, “36-Bit Physical Addressing Using the PAE PagingMechanism.”MCEMachine-Check Enable (bit 6 of CR4) — Enables the machine-checkexception when set; disables the machine-check exception when clear.See also: Chapter 14, “Machine-Check Architecture.”PGEPage Global Enable (bit 7 of CR4) — (Introduced in the P6 family processors.) Enables the global page feature when set; disables the global pagefeature when clear. The global page feature allows frequently used or sharedpages to be marked as global to all users (done with the global flag, bit 8, ina page-directory or page-table entry).
Global pages are not flushed from thetranslation-lookaside buffer (TLB) on a task switch or a write to register CR3.When enabling the global page feature, paging must be enabled (by settingthe PG flag in control register CR0) before the PGE flag is set. Reversing thissequence may affect program correctness, and processor performance willbe impacted.See also: Section 3.12, “Translation Lookaside Buffers (TLBs).”PCEPerformance-Monitoring Counter Enable (bit 8 of CR4) — Enablesexecution of the RDPMC instruction for programs or procedures running atany protection level when set; RDPMC instruction can be executed only atprotection level 0 when clear.OSFXSROperating System Support for FXSAVE and FXRSTOR instructions(bit 9 of CR4) — When set, this flag: (1) indicates to software that the operating system supports the use of the FXSAVE and FXRSTOR instructions, (2)enables the FXSAVE and FXRSTOR instructions to save and restore thecontents of the XMM and MXCSR registers along with the contents of the x87FPU and MMX registers, and (3) enables the processor to executeSSE/SSE2/SSE3 instructions, with the exception of the PAUSE, PREFETCHh,SFENCE, LFENCE, MFENCE, MOVNTI, and CLFLUSH.If this flag is clear, the FXSAVE and FXRSTOR instructions will save andrestore the contents of the x87 FPU and MMX instructions, but they may notsave and restore the contents of the XMM and MXCSR registers.
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