Volume 3A System Programming Guide_ Part 1 (794103), страница 27
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The processor then performs an access rights check on the call gate, comparingthe CPL with the privilege level of the call gate and the destination code segmentpointed to by the call gate.If access to the destination code segment is allowed, the processor gets the segmentselector for the destination code segment and an offset into that code segment fromthe call gate. If the call requires a change in privilege level, the processor alsoswitches to the stack for the targeted privilege level.
The segment selector for thenew stack is obtained from the TSS for the currently running task. Gates also facilitate transitions between 16-bit and 32-bit code segments, and vice versa.2.1.2.1Gates in IA-32e ModeIn IA-32e mode, the following descriptors are 16-byte descriptors (expanded to allowa 64-bit base): LDT descriptors, 64-bit TSSs, call gates, interrupt gates, and trapgates.Call gates facilitate transitions between 64-bit mode and compatibility mode.
Taskgates are not supported in IA-32e mode. On privilege level changes, stack segmentselectors are not read from the TSS. Instead, they are set to NULL.2.1.3Task-State Segments and Task GatesThe TSS (see Figure 2-1) defines the state of the execution environment for a task.It includes the state of general-purpose registers, segment registers, the EFLAGSregister, the EIP register, and segment selectors with stack pointers for three stacksegments (one stack for each privilege level). The TSS also includes the segmentselector for the LDT associated with the task and the page-table base address.All program execution in protected mode happens within the context of a task (calledthe current task).
The segment selector for the TSS for the current task is stored inthe task register. The simplest method for switching to a task is to make a call orjump to the new task. Here, the segment selector for the TSS of the new task is givenin the CALL or JMP instruction. In switching tasks, the processor performs thefollowing actions:1. Stores the state of the current task in the current TSS.1. The word “procedure” is commonly used in this document as a general term for a logical unit orblock of code (such as a program, procedure, function, or routine).2-6 Vol. 3SYSTEM ARCHITECTURE OVERVIEW2. Loads the task register with the segment selector for the new task.3.
Accesses the new TSS through a segment descriptor in the GDT.4. Loads the state of the new task from the new TSS into the general-purposeregisters, the segment registers, the LDTR, control register CR3 (page-table baseaddress), the EFLAGS register, and the EIP register.5. Begins execution of the new task.A task can also be accessed through a task gate. A task gate is similar to a call gate,except that it provides access (through a segment selector) to a TSS rather than acode segment.2.1.3.1Task-State Segments in IA-32e ModeHardware task switches are not supported in IA-32e mode. However, TSSs continueto exist. The base address of a TSS is specified by its descriptor.A 64-bit TSS holds the following information that is important to 64-bit operation:•••Stack pointer addresses for each privilege levelPointer addresses for the interrupt stack tableOffset address of the IO-permission bitmap (from the TSS base)The task register is expanded to hold 64-bit base addresses in IA-32e mode.
Seealso: Section 6.7, “Task Management in 64-bit Mode.”2.1.4Interrupt and Exception HandlingExternal interrupts, software interrupts and exceptions are handled through theinterrupt descriptor table (IDT). The IDT stores a collection of gate descriptors thatprovide access to interrupt and exception handlers. Like the GDT, the IDT is not asegment. The linear address for the base of the IDT is contained in the IDT register(IDTR).Gate descriptors in the IDT can be interrupt, trap, or task gate descriptors. To accessan interrupt or exception handler, the processor first receives an interrupt vector(interrupt number) from internal hardware, an external interrupt controller, or fromsoftware by means of an INT, INTO, INT 3, or BOUND instruction.
The interruptvector provides an index into the IDT. If the selected gate descriptor is an interruptgate or a trap gate, the associated handler procedure is accessed in a manner similarto calling a procedure through a call gate. If the descriptor is a task gate, the handleris accessed through a task switch.2.1.4.1Interrupt and Exception Handling IA-32e ModeIn IA-32e mode, interrupt descriptors are expanded to 16 bytes to support 64-bitbase addresses. This is true for 64-bit mode and compatibility mode.Vol.
3 2-7SYSTEM ARCHITECTURE OVERVIEWThe IDTR register is expanded to hold a 64-bit base address. Task gates are notsupported.2.1.5Memory ManagementSystem architecture supports either direct physical addressing of memory or virtualmemory (through paging). When physical addressing is used, a linear address istreated as a physical address. When paging is used: all code, data, stack, and systemsegments (including the GDT and IDT) can be paged with only the most recentlyaccessed pages being held in physical memory.The location of pages (sometimes called page frames) in physical memory iscontained in two types of system data structures: page directories and page tables.Both structures reside in physical memory (see Figure 2-1).The base physical address of the page directory is contained in control register CR3.An entry in a page directory contains the physical address of the base of a page table,access rights and memory management information.
An entry in a page tablecontains the physical address of a page frame, access rights and memory management information.To use this paging mechanism, a linear address is broken into three parts. The partsprovide separate offsets into the page directory, the page table, and the page frame.A system can have a single page directory or several. For example, each task canhave its own page directory.2.1.5.1Memory Management in IA-32e ModeIn IA-32e mode, physical memory pages are managed by a set of system data structures.
In compatibility mode and 64-bit mode, four levels of system data structuresare used. These include:•The page map level 4 (PML4) — An entry in a PML4 table contains the physicaladdress of the base of a page directory pointer table, access rights, and memorymanagement information. The base physical address of the PML4 is stored inCR3.•A set of page directory pointers — An entry in a page directory pointer tablecontains the physical address of the base of a page directory table, access rights,and memory management information.•Sets of page directories — An entry in a page directory table contains thephysical address of the base of a page table, access rights, and memorymanagement information.•Sets of page tables — An entry in a page table contains the physical address ofa page frame, access rights, and memory management information.2-8 Vol.
3SYSTEM ARCHITECTURE OVERVIEW2.1.6System RegistersTo assist in initializing the processor and controlling system operations, the systemarchitecture provides system flags in the EFLAGS register and several systemregisters:•The system flags and IOPL field in the EFLAGS register control task and modeswitching, interrupt handling, instruction tracing, and access rights. See also:Section 2.3, “System Flags and Fields in the EFLAGS Register.”•The control registers (CR0, CR2, CR3, and CR4) contain a variety of flags anddata fields for controlling system-level operations. Other flags in these registersare used to indicate support for specific processor capabilities within theoperating system or executive. See also: Section 2.5, “Control Registers.”•The debug registers (not shown in Figure 2-1) allow the setting of breakpoints foruse in debugging programs and systems software.
See also: Chapter 18,“Debugging and Performance Monitoring.”•The GDTR, LDTR, and IDTR registers contain the linear addresses and sizes(limits) of their respective tables. See also: Section 2.4, “Memory-ManagementRegisters.”•The task register contains the linear address and size of the TSS for the currenttask. See also: Section 2.4, “Memory-Management Registers.”•Model-specific registers (not shown in Figure 2-1).The model-specific registers (MSRs) are a group of registers available primarily tooperating-system or executive procedures (that is, code running at privilege level 0).These registers control items such as the debug extensions, the performance-monitoring counters, the machine- check architecture, and the memory type ranges(MTRRs).The number and function of these registers varies among different members of theIntel 64 and IA-32 processor families.
See also: Section 9.4, “Model-Specific Registers (MSRs),” and Appendix B, “Model-Specific Registers (MSRs).”Most systems restrict access to system registers (other than the EFLAGS register) byapplication programs. Systems can be designed, however, where all programs andprocedures run at the most privileged level (privilege level 0). In such a case, application programs would be allowed to modify the system registers.2.1.6.1System Registers in IA-32e ModeIn IA-32e mode, the four system-descriptor-table registers (GDTR, IDTR, LDTR, andTR) are expanded in hardware to hold 64-bit base addresses. EFLAGS becomes the64-bit RFLAGS register. CR0-CR4 are expanded to 64 bits.
CR8 becomes available.CR8 provides read-write access to the task priority register (TPR) so that the operating system can control the priority classes of external interrupts.In 64-bit mode, debug registers DR0–DR7 are 64 bits. In compatibility mode,address-matching in DR0-DR3 is also done at 64-bit granularity.Vol. 3 2-9SYSTEM ARCHITECTURE OVERVIEWOn systems that support IA-32e mode, the extended feature enable register(IA32_EFER) is available. This model-specific register controls activation of IA-32emode and other IA-32e mode operations. In addition, there are several modelspecific registers that govern IA-32e mode instructions:••••IA32_KernelGSbase — Used by SWAPGS instruction.IA32_LSTAR — Used by SYSCALL instruction.IA32_SYSCALL_FLAG_MASK — Used by SYSCALL instruction.IA32_STAR_CS — Used by SYSCALL and SYSRET instruction.2.1.7Other System ResourcesBesides the system registers and data structures described in the previous sections,system architecture provides the following additional resources:•Operating system instructions (see also: Section 2.6, “System InstructionSummary”).••Performance-monitoring counters (not shown in Figure 2-1).Internal caches and buffers (not shown in Figure 2-1).Performance-monitoring counters are event counters that can be programmed tocount processor events such as the number of instructions decoded, the number ofinterrupts received, or the number of cache loads.
See also: Section 18, “Debuggingand Performance Monitoring.”The processor provides several internal caches and buffers. The caches are used tostore both data and instructions. The buffers are used to store things like decodedaddresses to system and application segments and write operations waiting to beperformed. See also: Chapter 10, “Memory Cache Control.”2.2MODES OF OPERATIONThe IA-32 supports three operating modes and one quasi-operating mode:•Protected mode — This is the native operating mode of the processor. Itprovides a rich set of architectural features, flexibility, high performance andbackward compatibility to existing software base.•Real-address mode — This operating mode provides the programmingenvironment of the Intel 8086 processor, with a few extensions (such as theability to switch to protected or system management mode).•System management mode (SMM) — SMM is a standard architectural featurein all IA-32 processors, beginning with the Intel386 SL processor.
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