Volume 3A System Programming Guide_ Part 1 (794103), страница 31
Текст из файла (страница 31)
Also, theprocessor will generate an invalid opcode exception (#UD) if it attempts toexecute any SSE/SSE2/SSE3 instruction, with the exception of PAUSE,PREFETCHh, SFENCE, LFENCE, MFENCE, MOVNTI, and CLFLUSH. The operating system or executive must explicitly set this flag.2-24 Vol. 3SYSTEM ARCHITECTURE OVERVIEWNOTECPUID feature flags FXSR, SSE, SSE2, and SSE3 indicate availabilityof the FXSAVE/FXRESTOR instructions, SSE extensions, SSE2extensions, and SSE3 extensions respectively. The OSFXSR bitprovides operating system software with a means of enabling thesefeatures and indicating that the operating system supports thefeatures.OSXMMEXCPTOperating System Support for Unmasked SIMD Floating-Point Exceptions (bit 10 of CR4) — When set, indicates that the operating systemsupports the handling of unmasked SIMD floating-point exceptions throughan exception handler that is invoked when a SIMD floating-point exception(#XF) is generated.
SIMD floating-point exceptions are only generated bySSE/SSE2/SSE3 SIMD floating-point instructions.The operating system or executive must explicitly set this flag. If this flag isnot set, the processor will generate an invalid opcode exception (#UD)whenever it detects an unmasked SIMD floating-point exception.VMXEVMX-Enable Bit (bit 13 of CR4) — Enables VMX operation when set. SeeChapter 19, “Introduction to Virtual-Machine Extensions.”TPL2.5.1Task Priority Level (bit 3:0 of CR8) — This sets the threshold value corresponding to the highest-priority interrupt to be blocked.
A value of 0 meansall interrupts are enabled. This field is available in 64-bit mode. A value of 15means all interrupts will be disabled.CPUID Qualification of Control Register FlagsThe VME, PVI, TSD, DE, PSE, PAE, MCE, PGE, PCE, OSFXSR, and OSXMMEXCPT flagsin control register CR4 are model specific. All of these flags (except the PCE flag) canbe qualified with the CPUID instruction to determine if they are implemented on theprocessor before they are used.The CR8 register is available on processors that support Intel 64 architecture.2.6SYSTEM INSTRUCTION SUMMARYSystem instructions handle system-level functions such as loading system registers,managing the cache, managing interrupts, or setting up the debug registers.
Many ofthese instructions can be executed only by operating-system or executive procedures (that is, procedures running at privilege level 0). Others can be executed atany privilege level and are thus available to application programs.Vol. 3 2-25SYSTEM ARCHITECTURE OVERVIEWTable 2-2 lists the system instructions and indicates whether they are available anduseful for application programs. These instructions are described in the Intel® 64and IA-32 Architectures Software Developer’s Manual, Volumes 2A & 2B.Table 2-2. Summary of System InstructionsUseful toApplication?Protected fromApplication?InstructionDescriptionLLDTLoad LDT RegisterNoYesSLDTStore LDT RegisterNoNoLGDTLoad GDT RegisterNoYesSGDTStore GDT RegisterNoNoLTRLoad Task RegisterNoYesSTRStore Task RegisterNoNoLIDTLoad IDT RegisterNoYesSIDTStore IDT RegisterNoNoMOV CRnLoad and store control registersNoYesSMSWStore MSWYesNoLMSWLoad MSWNoYesCLTSClear TS flag in CR0NoYesARPLAdjust RPLLARLoad Access RightsYesNoLSLLoad Segment LimitYesNoVERRVerify for ReadingYesNoVERWVerify for WritingYesNoMOV DRnLoad and store debug registersNoYesINVDInvalidate cache, no writebackNoYesWBINVDInvalidate cache, with writebackNoYesINVLPGInvalidate TLB entryNoYesHLTHalt ProcessorNoYesLOCK (Prefix)Bus LockYesNoRSMReturn from system managementmodeNoYesRDMSR3Read Model-Specific RegistersNoYesWRMSR3Write Model-Specific RegistersNoYes2-26 Vol.
3Yes1, 5NoSYSTEM ARCHITECTURE OVERVIEWTable 2-2. Summary of System Instructions (Contd.)Useful toApplication?Protected fromApplication?InstructionDescriptionRDPMC4Read Performance-MonitoringCounterYesYes2RDTSC3Read Time-Stamp CounterYesYes2NOTES:1. Useful to application programs running at a CPL of 1 or 2.2. The TSD and PCE flags in control register CR4 control access to these instructions by applicationprograms running at a CPL of 3.3.
These instructions were introduced into the IA-32 Architecture with the Pentium processor.4. This instruction was introduced into the IA-32 Architecture with the Pentium Pro processor andthe Pentium processor with MMX technology.5. This instruction is not supported in 64-bit mode.2.6.1Loading and Storing System RegistersThe GDTR, LDTR, IDTR, and TR registers each have a load and store instruction forloading data into and storing data from the register:•LGDT (Load GDTR Register) — Loads the GDT base address and limit frommemory into the GDTR register.•SGDT (Store GDTR Register) — Stores the GDT base address and limit fromthe GDTR register into memory.•LIDT (Load IDTR Register) — Loads the IDT base address and limit frommemory into the IDTR register.•SIDT (Load IDTR Register — Stores the IDT base address and limit from theIDTR register into memory.•LLDT (Load LDT Register) — Loads the LDT segment selector and segmentdescriptor from memory into the LDTR.
(The segment selector operand can alsobe located in a general-purpose register.)•SLDT (Store LDT Register) — Stores the LDT segment selector from the LDTRregister into memory or a general-purpose register.•LTR (Load Task Register) — Loads segment selector and segment descriptorfor a TSS from memory into the task register. (The segment selector operand canalso be located in a general-purpose register.)•STR (Store Task Register) — Stores the segment selector for the current taskTSS from the task register into memory or a general-purpose register.The LMSW (load machine status word) and SMSW (store machine status word)instructions operate on bits 0 through 15 of control register CR0. These instructionsare provided for compatibility with the 16-bit Intel 286 processor.
Programs writtenVol. 3 2-27SYSTEM ARCHITECTURE OVERVIEWto run on 32-bit IA-32 processors should not use these instructions. Instead, theyshould access the control register CR0 using the MOV instruction.The CLTS (clear TS flag in CR0) instruction is provided for use in handling adevice-not-available exception (#NM) that occurs when the processor attempts toexecute a floating-point instruction when the TS flag is set. This instruction allowsthe TS flag to be cleared after the x87 FPU context has been saved, preventingfurther #NM exceptions.
See Section 2.5, “Control Registers,” for more informationon the TS flag.The control registers (CR0, CR1, CR2, CR3, CR4, and CR8) are loaded using the MOVinstruction. The instruction loads a control register from a general-purpose registeror stores the content of a control register in a general-purpose register.2.6.2Verifying of Access PrivilegesThe processor provides several instructions for examining segment selectorsand segment descriptors to determine if access to their associated segmentsis allowed. These instructions duplicate some of the automatic access rightsand type checking done by the processor, thus allowing operating-system orexecutive software to prevent exceptions from being generated.The ARPL (adjust RPL) instruction adjusts the RPL (requestor privilege level)of a segment selector to match that of the program or procedure thatsupplied the segment selector.
See Section 4.10.4, “Checking Caller AccessPrivileges (ARPL Instruction),” for a detailed explanation of the function anduse of this instruction. Note that ARPL is not supported in 64-bit mode.The LAR (load access rights) instruction verifies the accessibility of a speci-fied segment and loads access rights information from the segment’ssegment descriptor into a general-purpose register. Software can thenexamine the access rights to determine if the segment type is compatiblewith its intended use.
See Section 4.10.1, “Checking Access Rights (LARInstruction),” for a detailed explanation of the function and use of thisinstruction.The LSL (load segment limit) instruction verifies the accessibility of a speci-fied segment and loads the segment limit from the segment’s segmentdescriptor into a general-purpose register. Software can then compare thesegment limit with an offset into the segment to determine whether theoffset lies within the segment. See Section 4.10.3, “Checking That thePointer Offset Is Within Limits (LSL Instruction),” for a detailed explanationof the function and use of this instruction.The VERR (verify for reading) and VERW (verify for writing) instructionsverify if a selected segment is readable or writable, respectively, at a givenCPL.
See Section 4.10.2, “Checking Read/Write Rights (VERR and VERWInstructions),” for a detailed explanation of the function and use of thisinstruction.2-28 Vol. 3SYSTEM ARCHITECTURE OVERVIEW2.6.3Loading and Storing Debug RegistersInternal debugging facilities in the processor are controlled by a set of 8 debug registers (DR0-DR7). The MOV instruction allows setup data to be loaded to and storedfrom these registers.On processors that support Intel 64 architecture, debug registers DR0-DR7 are 64bits. In 32-bit modes and compatibility mode, writes to a debug register fill the upper32 bits with zeros. Reads return the lower 32 bits.
In 64-bit mode, the upper 32 bitsof DR6-DR7 are reserved and must be written with zeros. Writing one to any of theupper 32 bits causes an exception, #GP(0).In 64-bit mode, MOV DRn instructions read or write all 64 bits of a debug register(operand-size prefixes are ignored).
All 64 bits of DR0-DR3 are writable by software.However, MOV DRn instructions do not check that addresses written to DR0-DR3 arein the limits of the implementation. Address matching is supported only on validaddresses generated by the processor implementation.2.6.4Invalidating Caches and TLBsThe processor provides several instructions for use in explicitly invalidating its cachesand TLB entries. The INVD (invalidate cache with no writeback) instruction invalidates all data and instruction entries in the internal caches and sends a signal to theexternal caches indicating that they should be also be invalidated.The WBINVD (invalidate cache with writeback) instruction performs the same function as the INVD instruction, except that it writes back modified lines in its internalcaches to memory before it invalidates the caches.
After invalidating the internalcaches, WBINVD signals external caches to write back modified data and invalidatetheir contents.The INVLPG (invalidate TLB entry) instruction invalidates (flushes) the TLB entry fora specified page.2.6.5Controlling the ProcessorThe HLT (halt processor) instruction stops the processor until an enabled interrupt(such as NMI or SMI, which are normally enabled), a debug exception, the BINIT#signal, the INIT# signal, or the RESET# signal is received.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
