Volume 3A System Programming Guide_ Part 1 (794103), страница 26
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3ABOUT THIS MANUAL•Developer centers:http://www.intel.com/cd/ids/developer/asmo-na/eng/dc/index.htm•Processor support general link:http://www.intel.com/support/processors/•Software products and packages:http://www.intel.com/cd/software/products/asmo-na/eng/index.htm•Intel 64 and IA-32 processor manuals (printed or PDF downloads):http://developer.intel.com/products/processor/manuals/index.htm•Intel® Multi-Core Technology:http://developer.intel.com/multi-core/index.htm•Hyper-Threading Technology (HT Technology):http://developer.intel.com/technology/hyperthread/Vol.
3 1-11ABOUT THIS MANUAL1-12 Vol. 3CHAPTER 2SYSTEM ARCHITECTURE OVERVIEWIA-32 architecture (beginning with the Intel386 processor family) provides extensivesupport for operating-system and system-development software. This support offersmultiple modes of operation, which include:•Real mode, protected mode, virtual 8086 mode, and system management mode.These are sometimes referred to as legacy modes.Intel 64 architecture supports almost all the system programming facilities availablein IA-32 architecture and extends them to a new operating mode (IA-32e mode) thatsupports a 64-bit programming environment.
IA-32e mode allows software tooperate in one of two sub-modes:••64-bit mode supports 64-bit OS and 64-bit applicationsCompatibility mode allows most legacy software to run; it co-exists with 64-bitapplications under a 64-bit OS.The IA-32 system-level architecture and includes features to assist in the followingoperations:••••••••Memory managementProtection of software modulesMultitaskingException and interrupt handlingMultiprocessingCache managementHardware resource and power managementDebugging and performance monitoringThis chapter provides a description of each part of this architecture. It also describesthe system registers that are used to set up and control the processor at the systemlevel and gives a brief overview of the processor’s system-level (operating system)instructions.Many features of the system-level architectural are used only by system programmers.
However, application programmers may need to read this chapter and thefollowing chapters in order to create a reliable and secure environment for application programs.This overview and most subsequent chapters of this book focus on protected-modeoperation of the IA-32 architecture. IA-32e mode operation of the Intel 64 architecture, as it differs from protected mode operation, is also described.All Intel 64 and IA-32 processors enter real-address mode following a power-up orreset (see Chapter 9, “Processor Management and Initialization”).
Software thenVol. 3 2-1SYSTEM ARCHITECTURE OVERVIEWinitiates the switch from real-address mode to protected mode. If IA-32e mode operation is desired, software also initiates a switch from protected mode to IA-32emode.2.1OVERVIEW OF THE SYSTEM-LEVEL ARCHITECTURESystem-level architecture consists of a set of registers, data structures, and instructions designed to support basic system-level operations such as memory management, interrupt and exception handling, task management, and control of multipleprocessors.Figure 2-1 provides a summary of system registers and data structures that appliesto 32-bit modes. System registers and data structures that apply to IA-32e mode areshown in Figure 2-2.2-2 Vol.
3SYSTEM ARCHITECTURE OVERVIEWPhysical AddressEFLAGS RegisterControl RegistersCR4CR3CR2CR1CR0Task RegisterInterruptVectorCode, Data orStack SegmentLinear AddressTask-StateSegment (TSS)Segment SelectorRegisterGlobal DescriptorTable (GDT)Segment Sel.Seg. Desc.TSS Seg. Sel.TSS Desc.Interrupt HandlerCodeCurrentStackTSSSeg. Desc.Interrupt DescriptorTable (IDT)Task-StateSegment (TSS)TSS Desc.Interrupt GateTaskCodeDataStackLDT Desc.Task GateTaskCodeDataStackGDTRTrap GateLocal DescriptorTable (LDT)IDTRCall-GateSegment SelectorSeg. Desc.Call GateProtected ProcedureCodeCurrentStackTSSLDTRLinear Address SpaceDirLinear Addr.Exception HandlerCodeCurrentStackTSSLinear AddressTableOffsetPage DirectoryPage TablePg.
Dir. EntryPg. Tbl. EntryPagePhysical Addr.0CR3*This page mapping example is for 4-KByte pagesand the normal 32-bit physical address size.*Physical AddressFigure 2-1. IA-32 System-Level Registers and Data StructuresVol. 3 2-3SYSTEM ARCHITECTURE OVERVIEWRFLAGSPhysical AddressControl RegisterCR8CR4CR3CR2CR1CR0Task RegisterInterruptVectorCode, Data or StackSegment (Base =0)Linear AddressTask-StateSegment (TSS)Segment SelectorRegisterGlobal DescriptorTable (GDT)Segment Sel.Seg. Desc.TRTSS Desc.NULLSeg.
Desc.Interrupt DescriptorTable (IDT)Interr. HandlerSeg. Desc.Interrupt GateLDT Desc.GDTRTrap GateISTLocal DescriptorTable (LDT)NULLCall-GateSegment SelectorSeg. Desc.Call GateNULLLDTRLinear Address SpaceLinear Addr.CodeCurrent TSSStackInterrupt GateIDTRInterrupt HandlerCodeStackLinear AddressPML4 Dir. Pointer DirectoryPML4Pg. Dir. Ptr.Pg. Dir.EntryPML4.Entry0CR3*Page Dir.TableException HandlerCodeStackProtected ProcedureCodeStackOffsetPage TablePage TblEntryPagePhysicalAddr.This page mapping example is for 4-KByte pagesand 40-bit physical address size.*Physical AddressFigure 2-2.
System-Level Registers and Data Structures in IA-32e Mode2-4 Vol. 3SYSTEM ARCHITECTURE OVERVIEW2.1.1Global and Local Descriptor TablesWhen operating in protected mode, all memory accesses pass through either theglobal descriptor table (GDT) or an optional local descriptor table (LDT) as shown inFigure 2-1.
These tables contain entries called segment descriptors. Segmentdescriptors provide the base address of segments well as access rights, type, andusage information.Each segment descriptor has an associated segment selector. A segment selectorprovides the software that uses it with an index into the GDT or LDT (the offset of itsassociated segment descriptor), a global/local flag (determines whether the selectorpoints to the GDT or the LDT), and access rights information.To access a byte in a segment, a segment selector and an offset must be supplied.The segment selector provides access to the segment descriptor for the segment (inthe GDT or LDT).
From the segment descriptor, the processor obtains the baseaddress of the segment in the linear address space. The offset then provides thelocation of the byte relative to the base address. This mechanism can be used toaccess any valid code, data, or stack segment, provided the segment is accessiblefrom the current privilege level (CPL) at which the processor is operating. The CPL isdefined as the protection level of the currently executing code segment.See Figure 2-1. The solid arrows in the figure indicate a linear address, dashed linesindicate a segment selector, and the dotted arrows indicate a physical address. Forsimplicity, many of the segment selectors are shown as direct pointers to a segment.However, the actual path from a segment selector to its associated segment is alwaysthrough a GDT or LDT.The linear address of the base of the GDT is contained in the GDT register (GDTR);the linear address of the LDT is contained in the LDT register (LDTR).2.1.1.1Global and Local Descriptor Tables in IA-32e ModeGDTR and LDTR registers are expanded to 64-bits wide in both IA-32e sub-modes(64-bit mode and compatibility mode).
For more information: see Section 3.5.2,“Segment Descriptor Tables in IA-32e Mode.”Global and local descriptor tables are expanded in 64-bit mode to support 64-bit baseaddresses, (16-byte LDT descriptors hold a 64-bit base address and variousattributes).
In compatibility mode, descriptors are not expanded.2.1.2System Segments, Segment Descriptors, and GatesBesides code, data, and stack segments that make up the execution environment ofa program or procedure, the architecture defines two system segments: the taskstate segment (TSS) and the LDT. The GDT is not considered a segment because it isnot accessed by means of a segment selector and segment descriptor. TSSs and LDTshave segment descriptors defined for them.Vol. 3 2-5SYSTEM ARCHITECTURE OVERVIEWThe architecture also defines a set of special descriptors called gates (call gates,interrupt gates, trap gates, and task gates).
These provide protected gateways tosystem procedures and handlers that may operate at a different privilege level thanapplication programs and most procedures. For example, a CALL to a call gate canprovide access to a procedure in a code segment that is at the same or a numericallylower privilege level (more privileged) than the current code segment. To access aprocedure through a call gate, the calling procedure1 supplies the selector for the callgate.
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