Volume 3A System Programming Guide_ Part 1 (794103), страница 23
Текст из файла (страница 23)
. . . . . . . . . . .1-10Definitions of Primary Processor-Based VM-Execution Controls . . . . . . . . . . . . . . . .1-11Definitions of Secondary Processor-Based VM-Execution Controls . . . . . . . . . . . . .1-12Definitions of VM-Exit Controls. . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . .1-16Format of an MSR Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-17Definitions of VM-Entry Controls . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-18Format of the VM-Entry Interruption-Information Field . . . . . . . . . . . . . . . . . . . . . . . .1-19Format of Exit Reason . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-21Format of the VM-Exit Interruption-Information Field. . . . . . . . . . . . . . . . . . . . . . . . . .1-22Format of the IDT-Vectoring Information Field . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . .1-23Structure of VMCS Component Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-26Exit Qualification for Debug Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 1-5Exit Qualification for Task Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6Exit Qualification for Control-Register Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7Exit Qualification for MOV DR . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8Exit Qualification for I/O Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9Exit Qualification for APIC-Access VM Exits from Linear Accesses . . . . . . . . . . . . . .1-10Vol. 3A xxxvCONTENTSPAGETable 23-7.Table 23-8.Table 24-1.Table 24-2.Table 24-3.Table 24-4.Table 24-5.Table 24-6.Table 24-7.Table 24-8.Table 24-9.Table 25-1.Table A-1.Table A-2.Table A-3.Table A-4.Table A-5.Table A-6.Table A-7.Table A-9.Table A-8.Table A-10.Table A-11.Table A-12.Table A-13.Table A-14.Table A-15.Table B-1.Table B-2.Table B-3.Table B-4.Table B-5.Table B-6.Table B-7.Table B-8.Table B-9.Table C-1.Table E-1.xxxvi Vol.
3AFormat of the VM-Exit Instruction-Information Field as Used forVMCLEAR, VMPTRLD, VMPTRST, VMREAD, VMWRITE, and VMXON. . . . . . . . . . . . . 1-15Format of the VM-Exit Instruction-Information Field as Used for INS and OUTS . 1-17SMRAM State Save Map . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6ISMRAM State Save Map for Intel 64 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9Processor Register Initialization in SMM . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . 1-12I/O Instruction Information in the SMM State Save Map . . . . . . . . . . . . . . . . . . . . . . . 1-15I/O Instruction Type Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . 1-16Auto HALT Restart Flag Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19I/O Instruction Restart Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 1-21Exit Qualification for SMIs That Arrive Immediately After the Retirementof an I/O Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27Format of MSEG Header . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-33Operating Modes for Host and Guest Environments . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15Architectural Performance Events . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1Fixed-Function Performance Counter and Pre-defined Performance Events . . . . . 1-2Non-Architectural Performance Events in Processors Based on Intel CoreMicroarchitecture . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4Non-Architectural Performance Events in Intel Core Solo and Intel Core DuoProcessors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . 1-46Performance Monitoring Events Supported by Intel NetBurstMicroarchitecture for Non-Retirement Counting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-55Performance Monitoring Events For Intel NetBurst Microarchitecture forAt-Retirement Counting . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-86Intel NetBurst Microarchitecture Model-Specific Performance MonitoringEvents (For Model Encoding 3, 4 or 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-93List of Metrics Available for Execution Tagging (For Execution Event Only). .
. . . 1-94List of Metrics Available for Front_end Tagging (For Front_end Event Only). . . . 1-94List of Metrics Available for Replay Tagging (For Replay Event Only). . . . . . . . . . . 1-95Event Mask Qualification for Logical Processors . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . 1-97Performance Monitoring Events on Intel® Pentium® M Processors . . . . . . . . . . . 1-103Performance Monitoring Events Modified on Intel® Pentium® M Processors . . 1-105Events That Can Be Counted with the P6 Family PerformanceMonitoring Counters . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-107Events That Can Be Counted with Pentium ProcessorPerformance-Monitoring Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 1-124MSRs in Processors Based on Intel Core Microarchitecture . . . . . . . . . . . . . . . . . . . . . 1-1MSRs in the Pentium 4 and Intel Xeon Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25MSRs Unique to 64-bit Intel Xeon Processor MP withUp to an 8 MB L3 Cache1-73MSRs Unique to Intel Xeon Processor 7100 Series. . . . . .
. . . . . . . . . . . . . . . . . . . . . . 1-74MSRs in Intel Core Solo, Intel Core Duo Processors, and Dual-core IntelXeon Processor LV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-76MSRs in Pentium M Processors .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-95MSRs in the P6 Family Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-105MSRs in the Pentium Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 1-117IA-32 Architectural MSRs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-118Boot Phase IPI Message Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2Incremental Decoding Information: Processor Family 06HMachine Error Codes For Machine Check.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1CONTENTSPAGETable E-2.Table E-3.Table F-1.Table F-2.Table F-3.Table F-4.Table G-1.Table H-1.Table H-2.Table H-3.Table H-4.Table H-5.Table H-6.Table H-7.Table H-8.Table H-9.Table H-10.Table H-11.Table H-12.Table I-1.Table J-1.Incremental Decoding Information: Processor Family 0FHMachine Error Codes For Machine Check . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5Decoding Family 0FH Machine Check Codes for Memory Hierarchy Errors . . . . . . . . 1-7EOI Message (14 Cycles) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . 1-1Short Message (21 Cycles) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2Non-Focused Lowest Priority Message (34 Cycles) . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . 1-3APIC Bus Status Cycles Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5Memory Types Used For VMCS Access. . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . 1-2Encodings for 16-Bit Guest-State Fields (0000_10xx_xxxx_xxx0B) . . . . . . . . . . . . 1-1Encodings for 16-Bit Host-State Fields (0000_11xx_xxxx_xxx0B) . . . . . . . . . . . . . 1-2Encodings for 64-Bit Control Fields (0010_00xx_xxxx_xxxAb) . . . . . . . . . . . . . .
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