Volume 3A System Programming Guide_ Part 1 (794103), страница 22
Текст из файла (страница 22)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-55Parameters for the Presence Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-56Parameters for the Write Update Data Function . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . 9-57Parameters for the Control Update Sub-function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-62Parameters for the Read Microcode Update Data Function . . . . . . . . . . . . . . . . . . . . 9-63Mnemonic Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-63Return Code Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-65Characteristics of the Caches, TLBs, Store Buffer, and Write CombiningBuffer in Intel 64 and IA-32 Processors . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . 10-2Memory Types and Their Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7Methods of Caching Available in Intel Core 2 Duo, Intel Core Duo,Pentium M, Pentium 4, Intel Xeon, P6 Family, and Pentium Processors .
. . . . . . . . 10-8MESI Cache Line States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12Cache Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15Effective Page-Level Memory Type for Pentium Pro and Pentium IIProcessors . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-19Effective Page-Level Memory Types for Pentium III and More RecentProcessor Families . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-20Memory Types That Can Be Encoded in MTRRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-28Address Mapping for Fixed-Range MTRRs .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-32Selection of PAT Entries with PAT, PCD, and PWT Flags . . . . . . . . . . . . . . . . . . . . . . 10-46Memory Types That Can Be Encoded With PAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-46Memory Type Setting of PAT Entries Following a Power-up or Reset .
. . . . . . . . 10-47Action Taken By MMX Instructions for Different Combinations of EM, MPand TS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1Effects of MMX Instructions on x87 FPU State . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . 11-3Effect of the MMX, x87 FPU, and FXSAVE/FXRSTOR Instructions on thex87 FPU Tag Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4Action Taken for Combinations of OSFXSR, OSXMMEXCPT, SSE, SSE2,SSE3, EM, MP, and TS1 . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3Action Taken for Combinations of OSFXSR, SSSE3, EM, and TS . . . . . . . . . . . . . . . . 12-4On-Demand Clock Modulation Duty Cycle Field Encoding. . . . . .
. . . . . . . . . . . . . . . . 13-14Bits 54:53 in IA32_MCi_STATUS MSRs when IA32_MCG_CAP[11] = 1and UC = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . 14-7Overwrite Rules for Enabled Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9Extended Machine Check State MSRs in Processors Without Support forIntel 64 Architecture . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-11Extended Machine Check State MSRs In Processors With SupportFor Intel 64 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-11IA32_MCi_Status [15:0] Simple Error Code Encoding . . . . . . . . .
. . . . . . . . . . . . . . . . 14-17IA32_MCi_Status [15:0] Compound Error Code Encoding . . . . . . . . . . . . . . . . . . . . . 14-18Encoding for TT (Transaction Type) Sub-Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-19Level Encoding for LL (Memory Hierarchy Level) Sub-Field . . . . . . . . . . .
. . . . . . . . 14-19Encoding of Request (RRRR) Sub-Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-20Encodings of PP, T, and II Sub-Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 14-21Real-Address Mode Exceptions and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8Software Interrupt Handling Methods While in Virtual-8086 Mode. . . . . . . . . . . . 15-26Characteristics of 16-Bit and 32-Bit Program Modules . . . . . . .
. . . . . . . . . . . . . . . . . 16-1CONTENTSPAGETable 17-1.Table 17-2.Table 17-3.Table 18-1.Table 18-2.Table 18-3.Table 18-4.Table 18-5.Table 18-6.Table 18-7.Table 18-8.Table 18-9.Table 18-10.Table 18-11.Table 18-12.Table 18-13.Table 18-15.Table 18-14.Table 18-16.Table 18-17.Table 18-18.Table 18-19.Table 18-20.Table 18-21.Table 20-1.Table 20-2.Table 20-3.Table 20-4.Table 20-5.Table 20-6.Table 20-7.Table 20-8.Table 20-9.Table 20-10.Table 20-11.Table 20-12.Table 20-13.Table 20-14.Table 20-15.Table 23-1.Table 23-2.Table 23-3.Table 23-4.Table 23-5.Table 23-6.New Instruction in the Pentium Processor and Later IA-32 Processors .
. . . . . . . .17-5Recommended Values of the EM, MP, and NE Flags for Intel486 SXMicroprocessor/Intel 487 SX Math Coprocessor System . . . . . . . . . . . . . . . . . . . . . 17-22EM and MP Flag Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . 17-22Breakpoint Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-7Debug Exception Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . .18-9LBR MSR Stack Structure for the Pentium® 4 and the Intel® Xeon®Processor Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-19MSR_DEBUGCTLA, IA32_DEBUGCTL, MSR_DEBUGCLTB Flag Encodings . . . . . .
. 18-28CPL-Qualified Branch Trace Store Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-29UMask and Event Select Encodings for Pre-Defined ArchitecturalPerformance Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . 18-48Core Specificity Encoding within a Non-Architectural Umask . . . . . . . . . . . . . . . . . 18-50Agent Specificity Encoding within a Non-Architectural Umask . . . . . . . . . . . . . . . . 18-50HW Prefetch Qualification Encoding within a Non-Architectural Umask . . . . . . . 18-51MESI Qualification Definitions within a Non-Architectural Umask .
. . . . . . . . . . . . 18-51Bus Snoop Qualification Definitions within a Non-Architectural Umask. . . . . . . . 18-52Snoop Type Qualification Definitions within a Non-Architectural Umask . . . . . . 18-52Association of Fixed-Function Performance Counters withArchitectural Performance Events. .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-53PEBS Performance Events for Intel Core Microarchitecture . . . . . . . . . . . . . . . . . . 18-57At-Retirement Performance Events for Intel Core Microarchitecture . . . . . . . . . 18-57Requirements to Program PEBS .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-58Performance Counter MSRs and Associated CCCR and ESCR MSRs(Pentium 4 and Intel Xeon Processors) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-61Event Example . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-76CCR Names and Bit Positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-82Effect of Logical Processor and CPL Qualification for Logical-ProcessorSpecific (TS) Events . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-95Effect of Logical Processor and CPL Qualification for Non-logicalProcessor-specific (TI) Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-96Format of the VMCS Region. . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2Format of Access Rights . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4Format of Interruptibility State. . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6Format of Pending-Debug-Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8Definitions of Pin-Based VM-Execution Controls. . . . . . . . . . . . . . . . . . . .
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