Volume 3A System Programming Guide_ Part 1 (794103), страница 21
Текст из файла (страница 21)
. . . . . . . . . . . . . . . . . . . . . . . . . . 1-6SMM Revision Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18Auto HALT Restart Field . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19SMBASE Relocation Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20I/O Instruction Restart Field . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21VMX Transitions and States of VMCS in a Logical Processor . . . . . . . . . . . . . . . . . . . . 1-4Virtual TLB Scheme . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7Host External Interrupts and Guest Virtual Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5MP System With Multiple Pentium III Processors . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . 1-3CONTENTSPAGETABLESTable 2-1.Table 2-2.Table 3-1.Table 3-2.Table 3-3.Table 3-4.Table 3-5.Table 4-1.Table 4-2.Table 4-3.Table 4-4.Table 4-5.Table 4-6.Table 4-7.Table 4-8.Table 4-9.Table 4-10.Table 5-1.Table 5-2.Table 5-3.Table 5-4.Table 5-5.Table 5-6.Table 5-7.Table 5-8.Table 6-1.Table 6-2.Table 7-1.Table 7-2.Table 8-1.Table 8-2.Table 8-3.Table 8-4.Table 9-1.Table 9-2.Table 9-3.Table 9-4.Table 9-5.Table 9-6.Table 9-7.Action Taken By x87 FPU Instructions for Different Combinations ofEM, MP, and TS . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-21Summary of System Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-26Code- and Data-Segment Types . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-17System-Segment and Gate-Descriptor Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-19Page Sizes and Physical Address Sizes. . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-25Reserved Bit Checking When Execute Disable Bit is Disabled . . . . . . . . . . . . . . . . . . .3-48Reserved Bit Checking When Execute Disable Bit is Enabled . . . . . . . . . . . .
. . . . . . .3-49Privilege Check Rules for Call Gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2364-Bit-Mode Stack Layout After CALLF with CPL Change . . . . . . . . . . . . . . . . . . . . . .4-28Combined Page-Directory and Page-Table Protection. .
. . . . . . . . . . . . . . . . . . . . . . . .4-42Page Sizes and Physical Address Sizes Supported by Execute-Disable BitCapability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-43Extended Feature Enable MSR (IA32_EFER). . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . .4-44IA-32e Mode Page Level Protection Matrix with Execute-Disable Bit Capability .4-44Legacy PAE-Enabled 4-KByte Page Level Protection Matrix withExecute-Disable Bit Capability . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-45Legacy PAE-Enabled 2-MByte Page Level Protection with Execute-DisableBit Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-45IA-32e Mode Page Level Protection Matrix with Execute-Disable BitCapability Enabled . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-46Reserved Bit Checking WIth Execute-Disable Bit Capability Not Enabled . . . . . . . .4-47Protected-Mode Exceptions and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-3Priority Among Simultaneous Exceptions and Interrupts . . . . . . . . . . . . . . . . . . . . . . .5-11Debug Exception Conditions and Corresponding Exception Classes . . . . . . . . . . . . .5-29Interrupt and Exception Classes . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-38Conditions for Generating a Double Fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-39Invalid TSS Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . .5-42Alignment Requirements by Data Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-60SIMD Floating-Point Exceptions Priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . .5-65Exception Conditions Checked During a Task Switch . . . . . . . . . . . . . . . . . . . . . . . . . .6-15Effect of a Task Switch on Busy Flag, NT Flag, Previous Task Link Field,and TS Flag . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-17Initial APIC IDs for the Logical Processors in a System that has FourIntel Xeon MP Processors Supporting Hyper-Threading Technology . . . . . . . . . . . .7-38Initial APIC IDs for the Logical Processors in a System that has Two PhysicalProcessors Supporting Dual-Core and Hyper-Threading Technology . .
. . . . . . . . . .7-39Local APIC Register Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8ESR Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . .8-20Valid Combinations for the Pentium 4 and Intel Xeon ProcessorsLocal xAPIC Interrupt Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-27Valid Combinations for the P6 Family Processors’ Local APIC InterruptCommandRegister . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-28IA-32 Processor States Following Power-up, Reset, or INIT . . . . . . . . . . . . . . . . . . . . . 9-2Recommended Settings of EM and MP Flags on IA-32 Processors . . . . . . . . . . . . . .
. 9-7Software Emulation Settings of EM, MP, and NE Flags . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8Main Initialization Steps in STARTUP.ASM Source Listing . . . . . . . . . . . . . . . . . . . . . .9-21Relationship Between BLD Item and ASM Source File. . . . . . . . . . . . .
. . . . . . . . . . . . .9-35Microcode Update Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-38Microcode Update Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . .9-40Vol. 3A xxxiiiCONTENTSPAGETable 9-8.Table 9-9.Table 9-10.Table 9-11.Table 9-12.Table 9-13.Table 9-14.Table 9-15.Table 9-17.Table 9-16.Table 9-18.Table 10-1.Table 10-2.Table 10-3.Table 10-4.Table 10-5.Table 10-6.Table 10-7.Table 10-8.Table 10-9.Table 10-11.Table 10-10.Table 10-12.Table 11-1.Table 11-2.Table 11-3.Table 12-1.Table 12-2.Table 13-1.Table 14-1.Table 14-2.Table 14-3.Table 14-4.Table 14-5.Table 14-6.Table 14-7.Table 14-8.Table 14-9.Table 14-10.Table 15-1.Table 15-2.Table 16-1.xxxiv Vol.
3AExtended Processor Signature Table Header Structure . . . . . . . . . . . . . . . . . . . . . . . 9-41Processor Signature Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-41Processor Flags . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-43Microcode Update Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-48Microcode Update Functions. . . . . . . . . . . . . . . .
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
