Volume 3A System Programming Guide_ Part 1 (794103), страница 24
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. . . 1-2Encodings for 64-Bit Guest-State Fields (0010_10xx_xxxx_xxxAb) . . . . . . . . . . . . 1-3Encodings for 32-Bit Control Fields (0100_00xx_xxxx_xxx0B) . . . . . . . . . . . . . . . . . 1-4Encodings for 32-Bit Read-Only Data Fields (0100_01xx_xxxx_xxx0B) . . .
. . . . . . 1-5Encodings for 32-Bit Guest-State Fields(0100_10xx_xxxx_xxx0B)1-5Encodings for 32-Bit Host-State Field (0100_11xx_xxxx_xxx0B) . . . . . . . . . . . . . . 1-6Encodings for Natural-Width Control Fields (0110_00xx_xxxx_xxx0B). . . . . . . . . . 1-7Encodings for Natural-Width Read-Only Data Fields (0110_01xx_xxxx_xxx0B) . 1-7Encodings for Natural-Width Guest-State Fields (0110_10xx_xxxx_xxx0B) .
. . . . 1-8Encodings for Natural-Width Host-State Fields (0110_11xx_xxxx_xxx0B) . . . . . . 1-9Basic Exit Reasons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1VM-Instruction Error Numbers. . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1Vol. 3A xxxviiCONTENTSPAGExxxviii Vol. 3ACHAPTER 1ABOUT THIS MANUALThe Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A:System Programming Guide, Part 1 (order number 253668) and the Intel® 64 andIA-32 Architectures Software Developer’s Manual, Volume 3B: System ProgrammingGuide, Part 2 (order number 253669) are part of a set that describes the architectureand programming environment of Intel 64 and IA-32 Architecture processors.
Theother volumes in this set are:•Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: BasicArchitecture (order number 253665).•Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes2A & 2B: Instruction Set Reference (order numbers 253666 and 253667).The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1,describes the basic architecture and programming environment of Intel 64 and IA-32processors. The Intel® 64 and IA-32 Architectures Software Developer’s Manual,Volumes 2A & 2B, describe the instruction set of the processor and the opcode structure. These volumes apply to application programmers and to programmers whowrite operating systems or executives. The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 3A & 3B, describe the operating-system supportenvironment of Intel 64 and IA-32 processors.
These volumes target operatingsystem and BIOS designers. In addition, Intel® 64 and IA-32 Architectures SoftwareDeveloper’s Manual, Volume 3B, addresses the programming environment forclasses of software that host operating systems.1.1PROCESSORS COVERED IN THIS MANUALThis manual set includes information pertaining primarily to the most recent Intel®64 and IA-32 processors, which include:••••••••••Pentium® processorsP6 family processorsPentium® 4 processorsPentium® M processorsIntel® Xeon® processorsPentium® D processorsPentium® processor Extreme Editions64-bit Intel® Xeon® processorsIntel® Core™ Duo processorIntel® Core™ Solo processorVol. 3 1-1ABOUT THIS MANUAL•••••••••Dual-Core Intel® Xeon® processor LVIntel® Core™2 Duo processorIntel® Core™2 Quad processorIntel® Xeon® processor 3000 seriesIntel® Xeon® processor 5100 seriesIntel® Xeon® processor 5300 seriesIntel® Core™2 Extreme processorIntel® Core™2 Extreme Quad-core processorIntel® Xeon® processor 7100 seriesP6 family processors are IA-32 processors based on the P6 family microarchitecture.This includes the Pentium® Pro, Pentium® II, Pentium® III, and Pentium® III Xeon®processors.The Pentium® 4, Pentium® D, and Pentium® processor Extreme Editions are basedon the Intel NetBurst® microarchitecture.
Most early Intel® Xeon® processors arebased on the Intel NetBurst® microarchitecture.The Intel® Core™ Duo, Intel® Core™ Solo and dual-core Intel® Xeon® processor LVare based on an improved Pentium® M processor microarchitecture.The Intel® Xeon® processor 3000, 5100, and 5300 series, Intel® Core™2 Duo,Intel® Core™2 Quad and Intel® Core™2 Extreme processors are based on Intel®Core™ microarchitecture.P6 family, Pentium® M, Intel® Core™ Solo, Intel® Core™ Duo processors, dual-coreIntel® Xeon® processor LV, and early generations of Pentium 4 and Intel Xeonprocessors support IA-32 architecture.The Intel® Xeon® processor 3000, 5100, 5300 series, Intel® Core™2 Duo, Intel®Core™2 Extreme processors, Intel Core 2 Quad processors, newer generations ofPentium 4 and Intel Xeon processor family support Intel® 64 architecture.IA-32 architecture is the instruction set architecture and programming environmentfor Intel's 32-bit microprocessors. Intel® 64 architecture is the instruction set architecture and programming environment which is a superset of and compatible withIA-32 architecture.1.2OVERVIEW OF THE SYSTEM PROGRAMMING GUIDEA description of this manual’s content follows:Chapter 1 — About This Manual.
Gives an overview of all five volumes of theIntel® 64 and IA-32 Architectures Software Developer’s Manual. It also describesthe notational conventions in these manuals and lists related Intel manuals anddocumentation of interest to programmers and hardware designers.1-2 Vol. 3ABOUT THIS MANUALChapter 2 — System Architecture Overview. Describes the modes of operationused by Intel 64 and IA-32 processors and the mechanisms provided by the architectures to support operating systems and executives, including the system-orientedregisters and data structures and the system-oriented instructions. The steps necessary for switching between real-address and protected modes are also identified.Chapter 3 — Protected-Mode Memory Management. Describes the data structures, registers, and instructions that support segmentation and paging. The chapterexplains how they can be used to implement a “flat” (unsegmented) memory modelor a segmented memory model.Chapter 4 — Protection.
Describes the support for page and segment protectionprovided in the Intel 64 and IA-32 architectures. This chapter also explains theimplementation of privilege rules, stack switching, pointer validation, user andsupervisor modes.Chapter 5 — Interrupt and Exception Handling. Describes the basic interruptmechanisms defined in the Intel 64 and IA-32 architectures, shows how interruptsand exceptions relate to protection, and describes how the architecture handles eachexception type.
Reference information for each exception is given at the end of thischapter.Chapter 6 — Task Management. Describes mechanisms the IA-32 architectureprovides to support multitasking and inter-task protection.Chapter 7 — Multiple-Processor Management. Describes the instructions andflags that support multiple processors with shared memory, memory ordering, andHyper-Threading Technology.Chapter 8 — Advanced Programmable Interrupt Controller (APIC). Describesthe programming interface to the local APIC and gives an overview of the interfacebetween the local APIC and the I/O APIC.Chapter 9 — Processor Management and Initialization. Defines the state of anIntel 64 or IA-32 processor after reset initialization.
This chapter also explains how toset up an Intel 64 or IA-32 processor for real-address mode operation and protectedmode operation, and how to switch between modes.Chapter 10 — Memory Cache Control. Describes the general concept of cachingand the caching mechanisms supported by the Intel 64 or IA-32 architectures. Thischapter also describes the memory type range registers (MTRRs) and how they canbe used to map memory types of physical memory. Information on using the newcache control and memory streaming instructions introduced with the Pentium III,Pentium 4, and Intel Xeon processors is also given.Chapter 11 — Intel® MMX™ Technology System Programming.
Describesthose aspects of the Intel® MMX™ technology that must be handled and consideredat the system programming level, including: task switching, exception handling, andcompatibility with existing system environments.Chapter 12 — System Programming for Streaming SIMD Instruction Sets.Describes those aspects of SSE/SSE2/SSE3 extensions that must be handled andVol. 3 1-3ABOUT THIS MANUALconsidered at the system programming level, including task switching, exceptionhandling, and compatibility with existing system environments.Chapter 13 — Power and Thermal Management.
Describes the architecture’s powerand the thermal monitoring facilities.Chapter 14 — Machine-Check Architecture. Describes the machine-check architecture.Chapter 15 — 8086 Emulation. Describes the real-address and virtual-8086modes of the IA-32 architecture.Chapter 16 — Mixing 16-Bit and 32-Bit Code. Describes how to mix 16-bit and32-bit code modules within the same program or task.Chapter 17 — IA-32 Architecture Compatibility. Describes architecturalcompatibility among IA-32 processors.Chapter 18 — Debugging and Performance Monitoring. Describes the debugging registers and other debug mechanism provided in Intel 64 or IA-32 processors.This chapter also describes the time-stamp counter and the performance-monitoringcounters.Chapter 19 — Introduction to Virtual-Machine Extensions.
Describes the basicelements of virtual machine architecture and the virtual-machine extensions forIntel 64 and IA-32 Architectures.Chapter 20 — Virtual-Machine Control Structures. Describes components thatmanage VMX operation. These include the working-VMCS pointer and the controlling-VMCS pointer.Chapter 21— VMX Non-Root Operation. Describes the operation of a VMX nonroot operation. Processor operation in VMX non-root mode can be restrictedprogrammatically such that certain operations, events or conditions can cause theprocessor to transfer control from the guest (running in VMX non-root mode) to themonitor software (running in VMX root mode).Chapter 22 — VM Entries.
Describes VM entries. VM entry transitions the processorfrom the VMM running in VMX root-mode to a VM running in VMX non-root mode.VM-Entry is performed by the execution of VMLAUNCH or VMRESUME instructions.Chapter 23 — VM Exits. Describes VM exits. Certain events, operations or situations while the processor is in VMX non-root operation may cause VM-exit transitions.In addition, VM exits can also occur on failed VM entries.Chapter 24 — System Management. Describes Intel 64 and IA-32 architectures’system management mode (SMM) facilities.Chapter 25 — Virtual-Machine Monitoring Programming Considerations.Describes programming considerations for VMMs. VMMs manage virtual machines(VMs).Chapter 26 — Virtualization of System Resources.
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