Volume 3A System Programming Guide_ Part 1 (794103), страница 25
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Describes the virtualization of thesystem resources. These include: debugging facilities, address translation, physicalmemory, and microcode update facilities.1-4 Vol. 3ABOUT THIS MANUALChapter 27 — Handling Boundary Conditions in a Virtual Machine Monitor.Describes what a VMM must consider when handling exceptions, interrupts, errorconditions, and transitions between activity states.Appendix A — Performance-Monitoring Events. Lists the events that can becounted with the performance-monitoring counters and the codes used to selectthese events.
Both Pentium processor and P6 family processor events are described.Appendix B — Model-Specific Registers (MSRs). Lists the MSRs available in thePentium processors, the P6 family processors, the Pentium 4, Intel Xeon, Intel CoreSolo, Intel Core Duo processors, and Intel Core 2 processor family and describestheir functions.Appendix C — MP Initialization For P6 Family Processors. Gives an example ofhow to use of the MP protocol to boot P6 family processors in n MP system.Appendix D — Programming the LINT0 and LINT1 Inputs.
Gives an example ofhow to program the LINT0 and LINT1 pins for specific interrupt vectors.Appendix E — Interpreting Machine-Check Error Codes. Gives an example ofhow to interpret the error codes for a machine-check error that occurred on a P6family processor.Appendix F — APIC Bus Message Formats. Describes the message formats formessages transmitted on the APIC bus for P6 family and Pentium processors.Appendix G — VMX Capability Reporting Facility. Describes the VMX capabilityMSRs. Support for specific VMX features is determined by reading capability MSRs.Appendix H — Field Encoding in VMCS. Enumerates all fields in the VMCS andtheir encodings.
Fields are grouped by width (16-bit, 32-bit, etc.) and type (gueststate, host-state, etc.).Appendix I — VM Basic Exit Reasons. Describes the 32-bit fields that encodereasons for a VM exit. Examples of exit reasons include, but are not limited to: software interrupts, processor exceptions, software traps, NMIs, external interrupts, andtriple faults.Appendix J — VM Instruction Error Numbers. Describes the VM-instruction errorcodes generated by failed VM instruction executions (that have a valid working-VMCSpointer).1.3NOTATIONAL CONVENTIONSThis manual uses specific notation for data-structure formats, for symbolic representation of instructions, and for hexadecimal and binary numbers.
A review of thisnotation makes the manual easier to read.Vol. 3 1-5ABOUT THIS MANUAL1.3.1Bit and Byte OrderIn illustrations of data structures in memory, smaller addresses appear toward thebottom of the figure; addresses increase toward the top. Bit positions are numberedfrom right to left. The numerical value of a set bit is equal to two raised to the powerof the bit position. Intel 64 and IA-32 processors are “little endian” machines; thismeans the bytes of a word are numbered starting from the least significant byte.Figure 1-1 illustrates these conventions.1.3.2Reserved Bits and Software CompatibilityIn many register and memory layout descriptions, certain bits are marked asreserved. When bits are marked as reserved, it is essential for compatibility withfuture processors that software treat these bits as having a future, though unknown,effect. The behavior of reserved bits should be regarded as not only undefined, butunpredictable.
Software should follow these guidelines in dealing with reserved bits:•Do not depend on the states of any reserved bits when testing the values ofregisters which contain such bits. Mask out the reserved bits before testing.•Do not depend on the states of any reserved bits when storing to memory or to aregister.••Do not depend on the ability to retain information written into any reserved bits.When loading a register, always load the reserved bits with the values indicatedin the documentation, if any, or reload them with values previously read from thesame register.NOTEAvoid any software dependence upon the state of reserved bits inIntel 64 and IA-32 registers. Depending upon the values of reservedregister bits will make software dependent upon the unspecifiedmanner in which the processor handles these bits.
Programs thatdepend upon reserved values risk incompatibility with futureprocessors.1-6 Vol. 3ABOUT THIS MANUALHighest31AddressData Structure8 724 2316 15Byte 3Byte 2Byte 1Bit offset0Byte 02824201612840LowestAddressByte OffsetFigure 1-1. Bit and Byte Order1.3.3Instruction OperandsWhen instructions are represented symbolically, a subset of assembly language isused. In this subset, an instruction has the following format:label: mnemonic argument1, argument2, argument3where:••A label is an identifier which is followed by a colon.•The operands argument1, argument2, and argument3 are optional. Theremay be from zero to three operands, depending on the opcode.
When present,they take the form of either literals or identifiers for data items. Operandidentifiers are either reserved names of registers or are assumed to be assignedto data items declared in another part of the program (which may not be shownin the example).A mnemonic is a reserved name for a class of instruction opcodes which havethe same function.When two operands are present in an arithmetic or logical instruction, the rightoperand is the source and the left operand is the destination.For example:LOADREG: MOV EAX, SUBTOTALIn this example LOADREG is a label, MOV is the mnemonic identifier of an opcode,EAX is the destination operand, and SUBTOTAL is the source operand. Someassembly languages put the source and destination in reverse order.Vol.
3 1-7ABOUT THIS MANUAL1.3.4Hexadecimal and Binary NumbersBase 16 (hexadecimal) numbers are represented by a string of hexadecimal digitsfollowed by the character H (for example, F82EH). A hexadecimal digit is a characterfrom the following set: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, and F.Base 2 (binary) numbers are represented by a string of 1s and 0s, sometimesfollowed by the character B (for example, 1010B). The “B” designation is only used insituations where confusion as to the type of number might arise.1.3.5Segmented AddressingThe processor uses byte addressing. This means memory is organized and accessedas a sequence of bytes. Whether one or more bytes are being accessed, a byteaddress is used to locate the byte or bytes memory. The range of memory that canbe addressed is called an address space.The processor also supports segmented addressing. This is a form of addressingwhere a program may have many independent address spaces, called segments.For example, a program can keep its code (instructions) and stack in separatesegments.
Code addresses would always refer to the code space, and stackaddresses would always refer to the stack space. The following notation is used tospecify a byte address within a segment:Segment-register:Byte-addressFor example, the following segment address identifies the byte at address FF79H inthe segment pointed by the DS register:DS:FF79HThe following segment address identifies an instruction address in the code segment.The CS register points to the code segment and the EIP register contains the addressof the instruction.CS:EIP1.3.6Syntax for CPUID, CR, and MSR ValuesObtain feature flags, status, and system information by using the CPUID instruction,by checking control register bits, and by reading model-specific registers.
We aremoving toward a single syntax to represent this type of information. See Figure 1-2.1-8 Vol. 3ABOUT THIS MANUAL6\QWD[5HSUHVHQWDWLRQIRU&38,',QSXWDQG2XWSXW&38,'+(&;66(>ELW@ ,QSXWYDOXHIRU($;GHILQHVRXWSXW127(6RPHOHDYHVUHTXLUHLQSXWYDOXHVIRU($;DQG(&;,IRQO\RQHYDOXHLVSUHVHQW($;LVLPSOLHG2XWSXWUHJLVWHUDQGIHDWXUHIODJRUILHOGQDPHZLWKELWSRVLWLRQV9DOXHRUUDQJHRIRXWSXW)RU&RQWURO5HJLVWHU9DOXHV&526);65>ELW@ ([DPSOH&5QDPH)HDWXUHIODJRUILHOGQDPHZLWKELWSRVLWLRQV9DOXHRUUDQJHRIRXWSXW)RU0RGHO6SHFLILF5HJLVWHU9DOXHV,$B0,6&B(1$%/(6(1$%/()23&2'(>ELW@ ([DPSOH065QDPH)HDWXUHIODJRUILHOGQDPHZLWKELWSRVLWLRQV9DOXHRUUDQJHRIRXWSXW20Figure 1-2. Syntax for CPUID, CR, and MSR Data Presentation1.3.7ExceptionsAn exception is an event that typically occurs when an instruction causes an error.For example, an attempt to divide by zero generates an exception.
However, someexceptions, such as breakpoints, occur under other conditions. Some types of exceptions may provide error codes. An error code reports additional information about theerror. An example of the notation used to show an exception and error code is shownbelow:#PF(fault code)Vol.
3 1-9ABOUT THIS MANUALThis example refers to a page-fault exception under conditions where an error codenaming a type of fault is reported. Under some conditions, exceptions which produceerror codes may not be able to report an accurate code. In this case, the error codeis zero, as shown below for a general-protection exception:#GP(0)1.4RELATED LITERATURELiterature related to Intel 64 and IA-32 processors is listed on-line at:http://developer.intel.com/products/processor/index.htmSome of the documents listed at this web site can be viewed on-line; others can beordered. The literature available is listed by Intel processor and then by the followingliterature types: applications notes, data sheets, manuals, papers, and specificationupdates.See also:•••The data sheet for a particular Intel 64 or IA-32 processor•Intel® Fortran Compiler documentation and online helphttp://www.intel.com/cd/software/products/asmo-na/eng/index.htm•Intel® VTune™ Performance Analyzer documentation and online helphttp://www.intel.com/cd/software/products/asmo-na/eng/index.htm•Intel® 64 and IA-32 Architectures Software Developer’s Manual (in five volumes)http://developer.intel.com/products/processor/manuals/index.htm•Intel® 64 and IA-32 Architectures Optimization Reference Manualhttp://developer.intel.com/products/processor/manuals/index.htm•Intel® Processor Identification with the CPUID Instruction, AP-485http://www.intel.com/support/processors/sb/cs-009861.htm•Developing Multi-threaded Applications: A Platform Consistent Approach•Using Spin-Loops on Intel Pentium 4 Processor and Intel Xeon Processor MPhttp://www3.intel.com/cd/ids/developer/asmona/eng/dc/threading/knowledgebase/19083.htmThe specification update for a particular Intel 64 or IA-32 processorIntel® C++ Compiler documentation and online helphttp://www.intel.com/cd/software/products/asmo-na/eng/index.htmhttp://cachewww.intel.com/cd/00/00/05/15/51534_developing_multithreaded_applications.pdfMore relevant links are:•Software network link:http://softwarecommunity.intel.com/isn/home/1-10 Vol.
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