Volume 3A System Programming Guide_ Part 1 (794103), страница 29
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Special instructions are provided for loadingand storing these registers.Vol. 3 2-15SYSTEM ARCHITECTURE OVERVIEW47(79)System Table Registers16 150GDTR32(64)-bit Linear Base Address16-Bit Table LimitIDTR32(64)-bit Linear Base Address16-Bit Table LimitSystem SegmentRegisters150TaskRegisterLDTRSegment Descriptor Registers (Automatically Loaded)AttributesSeg. Sel.32(64)-bit Linear Base AddressSegment LimitSeg. Sel.32(64)-bit Linear Base AddressSegment LimitFigure 2-5. Memory Management Registers2.4.1Global Descriptor Table Register (GDTR)The GDTR register holds the base address (32 bits in protected mode; 64 bits inIA-32e mode) and the 16-bit table limit for the GDT.
The base address specifies thelinear address of byte 0 of the GDT; the table limit specifies the number of bytes inthe table.The LGDT and SGDT instructions load and store the GDTR register, respectively. Onpower up or reset of the processor, the base address is set to the default value of 0and the limit is set to 0FFFFH.
A new base address must be loaded into the GDTR aspart of the processor initialization process for protected-mode operation.See also: Section 3.5.1, “Segment Descriptor Tables.”2.4.2Local Descriptor Table Register (LDTR)The LDTR register holds the 16-bit segment selector, base address (32 bits inprotected mode; 64 bits in IA-32e mode), segment limit, and descriptor attributesfor the LDT.
The base address specifies the linear address of byte 0 of the LDTsegment; the segment limit specifies the number of bytes in the segment. See also:Section 3.5.1, “Segment Descriptor Tables.”The LLDT and SLDT instructions load and store the segment selector part of the LDTRregister, respectively. The segment that contains the LDT must have a segmentdescriptor in the GDT. When the LLDT instruction loads a segment selector in theLDTR: the base address, limit, and descriptor attributes from the LDT descriptor areautomatically loaded in the LDTR.When a task switch occurs, the LDTR is automatically loaded with the segmentselector and descriptor for the LDT for the new task.
The contents of the LDTR are notautomatically saved prior to writing the new LDT information into the register.On power up or reset of the processor, the segment selector and base address are setto the default value of 0 and the limit is set to 0FFFFH.2-16 Vol. 3SYSTEM ARCHITECTURE OVERVIEW2.4.3IDTR Interrupt Descriptor Table RegisterThe IDTR register holds the base address (32 bits in protected mode; 64 bits inIA-32e mode) and 16-bit table limit for the IDT.
The base address specifies the linearaddress of byte 0 of the IDT; the table limit specifies the number of bytes in the table.The LIDT and SIDT instructions load and store the IDTR register, respectively. Onpower up or reset of the processor, the base address is set to the default value of 0and the limit is set to 0FFFFH. The base address and limit in the register can then bechanged as part of the processor initialization process.See also: Section 5.10, “Interrupt Descriptor Table (IDT).”2.4.4Task Register (TR)The task register holds the 16-bit segment selector, base address (32 bits inprotected mode; 64 bits in IA-32e mode), segment limit, and descriptor attributesfor the TSS of the current task. The selector references the TSS descriptor in the GDT.The base address specifies the linear address of byte 0 of the TSS; the segment limitspecifies the number of bytes in the TSS.
See also: Section 6.2.4, “Task Register.”The LTR and STR instructions load and store the segment selector part of the taskregister, respectively. When the LTR instruction loads a segment selector in the taskregister, the base address, limit, and descriptor attributes from the TSS descriptorare automatically loaded into the task register.
On power up or reset of the processor,the base address is set to the default value of 0 and the limit is set to 0FFFFH.When a task switch occurs, the task register is automatically loaded with thesegment selector and descriptor for the TSS for the new task.
The contents of thetask register are not automatically saved prior to writing the new TSS informationinto the register.2.5CONTROL REGISTERSControl registers (CR0, CR1, CR2, CR3, and CR4; see Figure 2-6) determine operating mode of the processor and the characteristics of the currently executing task.These registers are 32 bits in all 32-bit modes and compatibility mode.In 64-bit mode, control registers are expanded to 64 bits. The MOV CRn instructionsare used to manipulate the register bits. Operand-size prefixes for these instructionsare ignored. The following is also true:•Bits 63:32 of CR0 and CR4 are reserved and must be written with zeros. Writinga nonzero value to any of the upper 32 bits results in a general-protectionexception, #GP(0).••All 64 bits of CR2 are writable by software.Bits 51:40 of CR3 are reserved and must be 0.Vol.
3 2-17SYSTEM ARCHITECTURE OVERVIEW•The MOV CRn instructions do not check that addresses written to CR2 and CR3are within the linear-address or physical-address limitations of the implementation.•Register CR8 is available in 64-bit mode only.The control registers are summarized below, and each architecturally defined controlfield in these control registers are described individually. In Figure 2-6, the width ofthe register in 64-bit mode is indicated in parenthesis (except for CR0).•CR0 — Contains system control flags that control operating mode and states ofthe processor.••CR1 — Reserved.•CR3 — Contains the physical address of the base of the page directory and twoflags (PCD and PWT). This register is also known as the page-directory baseregister (PDBR).
Only the most-significant bits (less the lower 12 bits) of the baseaddress are specified; the lower 12 bits of the address are assumed to be 0. Thepage directory must thus be aligned to a page (4-KByte) boundary. The PCD andPWT flags control caching of the page directory in the processor’s internal datacaches (they do not control TLB caching of page-directory information).CR2 — Contains the page-fault linear address (the linear address that caused apage fault).When using the physical address extension, the CR3 register contains the baseaddress of the page-directory-pointer table In IA-32e mode, the CR3 registercontains the base address of the PML4 table.See also: Section 3.8, “36-Bit Physical Addressing Using the PAE PagingMechanism.”•CR4 — Contains a group of flags that enable several architectural extensions,and indicate operating system or executive support for specific processor capabilities.
The control registers can be read and loaded (or modified) using the moveto-or-from-control-registers forms of the MOV instruction. In protected mode,the MOV instructions allow the control registers to be read or loaded (at privilegelevel 0 only). This restriction means that application programs or operatingsystem procedures (running at privilege levels 1, 2, or 3) are prevented fromreading or loading the control registers.•CR8 — Provides read and write access to the Task Priority Register (TPR). Itspecifies the priority threshold value that operating systems use to control thepriority class of external interrupts allowed to interrupt the processor.
Thisregister is available only in 64-bit mode. However, interrupt filtering continues toapply in compatibility mode.2-18 Vol. 3SYSTEM ARCHITECTURE OVERVIEW31(63)13 12 11 10 9 8 7 6 5 4 3 2 1 0VM 0XEReserved (set to 0)0T P VP P M P PC G C A S D S V ME D I EE E E E ECR4OSXMMEXCPTOSFXSR31(63)12 115 4 3 2P PC WD TPage-Directory Base31(63)CR3(PDBR)0Page-Fault Linear AddressCR231(63)0CR131 30 29 28P C NG D W19 18 17 16 15AM6 5 4 3 2 1 0WPN E T E M PE T S M P ECR0ReservedFigure 2-6. Control RegistersWhen loading a control register, reserved bits should always be set to the valuespreviously read. The flags in control registers are:PGPaging (bit 31 of CR0) — Enables paging when set; disables paging whenclear.
When paging is disabled, all linear addresses are treated as physicaladdresses. The PG flag has no effect if the PE flag (bit 0 of register CR0) isnot also set; setting the PG flag when the PE flag is clear causes a generalprotection exception (#GP). See also: Section 3.6, “Paging (Virtual Memory)Overview.”On Intel 64 processors, enabling and disabling IA-32e mode operation alsorequires modifying CR0.PG.CDCache Disable (bit 30 of CR0) — When the CD and NW flags are clear,caching of memory locations for the whole of physical memory in theprocessor’s internal (and external) caches is enabled. When the CD flag isset, caching is restricted as described in Table 10-5. To prevent the processorfrom accessing and updating its caches, the CD flag must be set and thecaches must be invalidated so that no cache hits can occur.Vol. 3 2-19SYSTEM ARCHITECTURE OVERVIEWSee also: Section 10.5.3, “Preventing Caching,” and Section 10.5, “CacheControl.”NWNot Write-through (bit 29 of CR0) — When the NW and CD flags areclear, write-back (for Pentium 4, Intel Xeon, P6 family, and Pentium processors) or write-through (for Intel486 processors) is enabled for writes that hitthe cache and invalidation cycles are enabled.
See Table 10-5 for detailedinformation about the affect of the NW flag on caching for other settings ofthe CD and NW flags.AMAlignment Mask (bit 18 of CR0) — Enables automatic alignment checkingwhen set; disables alignment checking when clear. Alignment checking isperformed only when the AM flag is set, the AC flag in the EFLAGS register isset, CPL is 3, and the processor is operating in either protected or virtual8086 mode.WPWrite Protect (bit 16 of CR0) — Inhibits supervisor-level procedures fromwriting into user-level read-only pages when set; allows supervisor-levelprocedures to write into user-level read-only pages when clear (regardless ofthe U/S bit setting; see Section 3.7.6).
This flag facilitates implementation ofthe copy-on-write method of creating a new process (forking) used by operating systems such as UNIX.NENumeric Error (bit 5 of CR0) — Enables the native (internal) mechanismfor reporting x87 FPU errors when set; enables the PC-style x87 FPU errorreporting mechanism when clear. When the NE flag is clear and the IGNNE#input is asserted, x87 FPU errors are ignored. When the NE flag is clear andthe IGNNE# input is deasserted, an unmasked x87 FPU error causes theprocessor to assert the FERR# pin to generate an external interrupt and tostop instruction execution immediately before executing the next waitingfloating-point instruction or WAIT/FWAIT instruction.The FERR# pin is intended to drive an input to an external interruptcontroller (the FERR# pin emulates the ERROR# pin of the Intel 287 andIntel 387 DX math coprocessors).
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