Volume 3A System Programming Guide_ Part 1 (794103), страница 33
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The base address plus the offset thus forms a linear address in theprocessor’s linear address space.Logical Address(or Far Pointer)SegmentSelectorOffsetLinear AddressSpaceGlobal DescriptorTable (GDT)DirLinear AddressTableOffsetSegmentPage TableSegmentDescriptorPage DirectoryLin. Addr.PhysicalAddressSpacePagePhy. Addr.EntryEntrySegmentBase AddressPageSegmentationPagingFigure 3-1. Segmentation and PagingIf paging is not used, the linear address space of the processor is mapped directlyinto the physical address space of processor. The physical address space is defined asthe range of addresses that the processor can generate on its address bus.Because multitasking computing systems commonly define a linear address spacemuch larger than it is economically feasible to contain all at once in physical memory,some method of “virtualizing” the linear address space is needed.
This virtualizationof the linear address space is handled through the processor’s paging mechanism.Paging supports a “virtual memory” environment where a large linear address spaceis simulated with a small amount of physical memory (RAM and ROM) and some disk3-2 Vol. 3PROTECTED-MODE MEMORY MANAGEMENTstorage. When using paging, each segment is divided into pages (typically 4 KByteseach in size), which are stored either in physical memory or on the disk.
The operating system or executive maintains a page directory and a set of page tables to keeptrack of the pages. When a program (or task) attempts to access an address locationin the linear address space, the processor uses the page directory and page tables totranslate the linear address into a physical address and then performs the requestedoperation (read or write) on the memory location.If the page being accessed is not currently in physical memory, the processor interrupts execution of the program (by generating a page-fault exception). The operating system or executive then reads the page into physical memory from the diskand continues executing the program.When paging is implemented properly in the operating-system or executive, theswapping of pages between physical memory and the disk is transparent to thecorrect execution of a program.
Even programs written for 16-bit IA-32 processorscan be paged (transparently) when they are run in virtual-8086 mode.3.2USING SEGMENTSThe segmentation mechanism supported by the IA-32 architecture can be used toimplement a wide variety of system designs. These designs range from flat modelsthat make only minimal use of segmentation to protect programs to multisegmented models that employ segmentation to create a robust operating environment in which multiple programs and tasks can be executed reliably.The following sections give several examples of how segmentation can be employedin a system to improve memory management performance and reliability.3.2.1Basic Flat ModelThe simplest memory model for a system is the basic “flat model,” in which the operating system and application programs have access to a continuous, unsegmentedaddress space.
To the greatest extent possible, this basic flat model hides thesegmentation mechanism of the architecture from both the system designer and theapplication programmer.To implement a basic flat memory model with the IA-32 architecture, at least twosegment descriptors must be created, one for referencing a code segment and onefor referencing a data segment (see Figure 3-2).
Both of these segments, however,are mapped to the entire linear address space: that is, both segment descriptorshave the same base address value of 0 and the same segment limit of 4 GBytes. Bysetting the segment limit to 4 GBytes, the segmentation mechanism is kept fromgenerating exceptions for out of limit memory references, even if no physicalmemory resides at a particular address. ROM (EPROM) is generally located at the topof the physical address space, because the processor begins execution atVol. 3 3-3PROTECTED-MODE MEMORY MANAGEMENTFFFF_FFF0H. RAM (DRAM) is placed at the bottom of the address space because theinitial base address for the DS data segment after reset initialization is 0.3.2.2Protected Flat ModelThe protected flat model is similar to the basic flat model, except the segment limitsare set to include only the range of addresses for which physical memory actuallyexists (see Figure 3-3).
A general-protection exception (#GP) is then generated onany attempt to access nonexistent memory. This model provides a minimum level ofhardware protection against some kinds of program bugs.Linear Address Space(or Physical Memory)SegmentRegistersCSCodeCode- and Data-SegmentDescriptorsNot PresentSSDSESFFFFFFFFHAccessLimitBase AddressData andStack0FSGSFigure 3-2. Flat ModelSegmentRegistersSegmentDescriptorsLinear Address Space(or Physical Memory)AccessLimitBase AddressCodeFFFFFFFFHCSNot PresentESSSDSFSMemory I/OAccessLimitBase AddressData andStackGS0Figure 3-3.
Protected Flat Model3-4 Vol. 3PROTECTED-MODE MEMORY MANAGEMENTMore complexity can be added to this protected flat model to provide more protection. For example, for the paging mechanism to provide isolation between user andsupervisor code and data, four segments need to be defined: code and datasegments at privilege level 3 for the user, and code and data segments at privilegelevel 0 for the supervisor. Usually these segments all overlay each other and start ataddress 0 in the linear address space. This flat segmentation model along with asimple paging structure can protect the operating system from applications, and byadding a separate paging structure for each task or process, it can also protect applications from each other.
Similar designs are used by several popular multitaskingoperating systems.3.2.3Multi-Segment ModelA multi-segment model (such as the one shown in Figure 3-4) uses the full capabilities of the segmentation mechanism to provided hardware enforced protection ofcode, data structures, and programs and tasks. Here, each program (or task) is givenits own table of segment descriptors and its own segments. The segments can becompletely private to their assigned programs or shared among programs. Access toall segments and to the execution environments of individual programs running onthe system is controlled by hardware.Vol.
3 3-5PROTECTED-MODE MEMORY MANAGEMENTSegmentRegistersSegmentDescriptorsLinear Address Space(or Physical Memory)CSAccessLimitBase AddressStackSSAccessLimitBase AddressDSAccessLimitBase AddressESAccessLimitBase AddressFSAccessLimitBase AddressGSAccessLimitBase AddressAccessLimitBase AddressCodeDataDataDataAccessLimitBase AddressAccessLimitBase AddressDataAccessLimitBase AddressFigure 3-4. Multi-Segment ModelAccess checks can be used to protect not only against referencing an address outsidethe limit of a segment, but also against performing disallowed operations in certainsegments.
For example, since code segments are designated as read-only segments,hardware can be used to prevent writes into code segments. The access rights information created for segments can also be used to set up protection rings or levels.Protection levels can be used to protect operating-system procedures from unauthorized access by application programs.3.2.4Segmentation in IA-32e ModeIn IA-32e mode of Intel 64 architecture, the effects of segmentation depend onwhether the processor is running in compatibility mode or 64-bit mode.
In compatibility mode, segmentation functions just as it does using legacy 16-bit or 32-bitprotected mode semantics.3-6 Vol. 3PROTECTED-MODE MEMORY MANAGEMENTIn 64-bit mode, segmentation is generally (but not completely) disabled, creating aflat 64-bit linear-address space.
The processor treats the segment base of CS, DS,ES, SS as zero, creating a linear address that is equal to the effective address. The FSand GS segments are exceptions. These segment registers (which hold the segmentbase) can be used as an additional base registers in linear address calculations. Theyfacilitate addressing local data and certain operating system data structures.Note that the processor does not perform segment limit checks at runtime in 64-bitmode.3.2.5Paging and SegmentationPaging can be used with any of the segmentation models described in Figures 3-2,3-3, and 3-4.
The processor’s paging mechanism divides the linear address space(into which segments are mapped) into pages (as shown in Figure 3-1). These linearaddress-space pages are then mapped to pages in the physical address space. Thepaging mechanism offers several page-level protection facilities that can be usedwith or instead of the segment-protection facilities. For example, it lets read-writeprotection be enforced on a page-by-page basis. The paging mechanism alsoprovides two-level user-supervisor protection that can also be specified on a pageby-page basis.3.3PHYSICAL ADDRESS SPACEIn protected mode, the IA-32 architecture provides a normal physical address spaceof 4 GBytes (232 bytes).
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